Array and pitch of non-volatile memory cells
View Patent ↗An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.
1. An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell is formed in a semiconductor substrate of a first conductivity type, with a first region of a second conductivity type along the surface of the substrate, a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region defining a channel region therebetween, a floating gate over a portion of the channel region, a coupling gate over the floating gate, a word gate over another portion of the channel region and adjacent to and separated from the floating gate, and an erase gate over the second region adjacent to and separated from the floating gate, wherein cells in the same column have a common bit line connected to the first regions of memory cells in the same column, said array comprising:
a first and second sub arrays of memory cells arranged adjacent to one another in the same row;
a first decoder to one side of the first sub array in the same row as the first sub array;
a second decoder to another side of the second sub array in the same row as said second sub array;
a first coupling gate line connected to the second decoder and to only the coupling gate of the memory cells in the first sub array;
a second coupling gate line, different from the first coupling gate line, connected to the second decoder and to only the coupling gate of the memory cells in the second sub array;
a word line connected to the first decoder and to the word gate of the memory cells of said first and second sub arrays;
a first erase gate line connected to the second decoder and to only the erase gate of the memory cells of said first sub array; and
a second erase gate line connected to the second decoder and to only the erase gate of the memory cells of said second sub array.
2. The array of claim 1 further comprising:
a first source line connected to the second decoder and to only the second region of the memory cells in the first sub array;
a second source line, different from the first source line, connected to the second decoder and to only the second region of the memory cells in the second sub array.
3. The array of claim 2 further comprising:
A control loop circuit connected to the first source line through the second decoder for supplying a high voltage to the first source line.
4. The array of claim 3 further comprising a third source line connected only to the second region of memory cells only in the first sub-array for detecting a detected voltage of said second region of memory cells in the first sub-array and for supplying said detected voltage to said control loop circuit.
5. The array of claim 1 further comprising:
a source line connected to the second decoder and to the second region of memory cells in the first and second sub arrays.
6. The array of claim 1 wherein said second decoder supplies high voltage to said erase gate and said coupling gate lines.
7. The array of claim 6 wherein said second decoder further comprising first current limiting means for limiting current flowing to said first coupling gate line, and for limiting current flowing to said second coupling gate line.
8. The array of claim 7 wherein said second decoder further comprising current limiting means for limiting current flowing to said first erase gate line, and for limiting current flowing to said second erase gate line.
9. An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations, wherein cells in the same column have a common bit line connected to the first terminal of memory cells in the same column, said array comprising:
a first and second sub arrays of memory cells arranged adjacent to one another in the same row;
a first decoder to one side of the first sub array in the same row as the first sub array;
a second decoder to another side of the second sub array in the same row as said second sub array;
a first high voltage line connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array;
a second high voltage line, different from the first high voltage line, connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array; and
a low voltage line connected to the first decoder and to the thirds terminal of the memory cells in the same row of said first and second sub arrays.
10. The array of claim 9 wherein said second decoder further comprising:
current limiting means for limiting current flow through said first high voltage line and through said second high voltage line.
11. An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell is formed in a semiconductor substrate of a first conductivity type, with a first region of a second conductivity type along the surface of the substrate, a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region defining a channel region therebetween, a floating gate over a portion of the channel region, a coupling gate over the floating gate, a word gate over another portion of the channel region and adjacent to and separated from the floating gate, and an erase gate over the second region adjacent to and separated from the floating gate, wherein cells in the same column have a common bit line connected to the first regions of memory cells in the same column, said array comprising:
a first and second sub arrays of memory cells arranged in the same row;
a first decoder to one side of the first sub array in the same row as the first sub array;
a second decoder to another side of the second sub array in the same row as said second sub array;
a third decoder;
a first source line connected to the third decoder and to only the second region of the memory cells in the first sub array;
a second source line, different from the first source line, connected to the second decoder and to only the second region of the memory cells in the second sub array;
a first coupling gate line connected to the third decoder and to only the coupling gate of the memory cells in the first sub array;
a second coupling gate line, different from the first coupling gate line, connected to the second decoder and to only the coupling gate of the memory cells in the second sub array;
a word line connected to the first decoder and to the word gate of the memory cells of said first and second sub arrays;
a first erase gate line connected to the third decoder and to the erase gate of the memory cells of said first sub array; and
a second erase gate line connected to the second decoder and to the erase gate of the memory cells of said second sub array.
12. The array of claim 11 further comprising one or more signals lines connecting the second decoder to the third decoder for supplying partially decoded address signals to said third decoder.
13. The array of claim 12 wherein said third decoder is between the first decoder and the first sub array.
14. The array of claim 12 wherein said third decoder is between the first sub array and the second sub array.
15. The array of claim 12 wherein said second decoder supplies high voltage to said second source line, said second coupling gate line and said second erase gate line.
16. The array of claim 15 wherein said second decoder further comprising:
first current limiting means for limiting current flowing through said second coupling gate line; and
second current limiting means for limiting current flowing through said second erase gate line.
17. The array of claim 12 wherein said third decoder supplies high voltage to said first source line, said first coupling gate line and said first erase gate line.
18. The array of claim 17 wherein said third decoder further comprising:
first current limiting means for limiting current flowing through said second coupling gate line; and
second current limiting means for limiting current flowing through said second erase gate line.
19. An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell is formed in a semiconductor substrate of a first conductivity type, with a first region of a second conductivity type along the surface of the substrate, a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region defining a channel region therebetween, a floating gate over a portion of the channel region, a coupling gate over the floating gate, a word gate over another portion of the channel region and adjacent to and separated from the floating gate, and an erase gate over the second region adjacent to and separated from the floating gate, wherein cells in the same column have a common bit line connected to the first regions of memory cells in the same column, said array comprising:
a first and second sub arrays of memory cells arranged in the same row;
a first decoder to one side of the first sub array in the same row as the first sub array;
a second decoder;
a third decoder between said first and second sub arrays;
one or more signals lines connecting the second decoder to the third decoder for supplying partially decoded address signals to said third decoder;
a first source line connected to the third decoder and to only the second region of the memory cells in the first sub array;
a second source line connected to the second decoder and to only the second region of the memory cells in the second sub array;
a first coupling gate line connected to the third decoder and to only the coupling gate of the memory cells in the first sub array;
a second coupling gate line connected to the second decoder and to only the coupling gate of the memory cells in the second sub array;
a word line connected to the first decoder and to the word gate of the memory cells of said first and second sub arrays;
a first erase gate line connected to the third decoder and to the erase gate of the memory cells of said first sub array; and
a second erase gate line connected to the second decoder and to the erase gate of the memory cells of said second sub array.
20. The array of claim 19 wherein said second decoder is to another side of the second sub array in the same row as the first sub array.
21. The array of claim 19 wherein said second decoder is between said third decoder and said second sub array.
22. The array of claim 19 wherein said second decoder further comprising:
a first transistor for limiting current flowing through said second coupling gate line; and
a second transistor for limiting current flowing through said second erase gate line.
23. An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage: is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations, wherein cells in the same column have a common bit line connected to the first terminal of memory cells in the same column, said array comprising:
a first and second sub arrays of memory cells arranged adjacent to one another in the same row;
a first decoder to one side of the first sub array in the same row as the first sub array and providing low voltage only to low voltage terminals of the memory cells;
a second decoder to another side of the second sub array in the same row as said second sub array and providing high voltage only to high voltage terminals of to memory cells.
24. The array of claim 23 further comprising:
a first high voltage line connected to the second decoder and to only to second terminal of the memory cells in the first sub array;
a second high voltage line, different from the first high voltage line, connected to the second decoder and to only the second terminal of the memory cells in the second sub array.
25. The array of claim 24 further comprising:
a low voltage line connected to the first decoder and to the third terminal of the memory cells of said first and second sub arrays.
26. The array of claim 23 wherein said second decoder further comprising:
a current limiting transistor for limiting the current flowing through said second high voltage line.
27. An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations, wherein cells in the same column have a common bit line connected to the first terminal of memory cells in the same column, said array comprising:
a first and second sub arrays of memory cells arranged adjacent to one another in the same row;
a first decoder to one side of the first sub array in the same row as the first sub array;
a second decoder to another side of the second sub array in the same row as said second sub array; and
a third decoder in between the first decoder and the second decoder, wherein said third decoder for receiving predecoded signals from said second decoder.
28. The array of claim 27 wherein said first decoder providing first decoded signals to memory cells in said first and said second sub arrays;
wherein said second decoder providing second decoded signals only to said second sub array; and
wherein said third decoder providing third decoded signals only to said third sub array.
29. The array of claim 28 wherein said first decoded signals are low voltage signals.
30. The array of claim 28 wherein said second decoded signals are low voltage signals and high voltage signals.
31. The array of claim 28 wherein said third decoded signals are only high voltage signals.