Method of forming split-gate memory cell array along with low and high voltage logic devices
View Patent ↗A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.
1. A method of forming a memory device, comprising:
providing a silicon substrate, wherein the substrate has a memory area, an LV area and an HV area which are insulated from each other by insulation material extending into a surface of the substrate, and wherein the substrate has a first conductivity type;
forming pairs of spaced apart memory stacks on the substrate and in the memory area, wherein each memory stack includes:
a floating gate disposed over and insulated from the substrate, and
a control gate disposed over and insulated from the floating gate;
forming a first conductive layer over and insulated from the substrate in the memory area, the LV area and the HV area, wherein the first conductive layer extends up and over the pairs of memory stacks;
forming a first insulation layer on the first conductive layer in the memory area, the LV area and the HV area;
removing the first insulation layer from the memory area and the HV area, while maintaining the first insulation layer in the LV area;
performing a conductive material deposition to thicken the first conductive layer in the memory area and the HV area, and to form a second conductive layer on the first insulation layer in the LV area;
performing an etch to thin the first conductive layer in the memory area and the HV area, and to remove the second conductive layer in the LV area, wherein a top surface of the first conductive layer in the memory area and the HV area is higher than a bottom surface of the first insulation layer in the LV area;
removing the first insulation layer from the LV area; and
patterning the first conductive layer to form blocks of the first conductive layer in the memory area, the LV area and the HV area, wherein the blocks of the first conductive layer in the LV area have a height less than that of the blocks of the first conductive layer in the HV area.
2. The method of claim 1 , further comprising:
performing a first implantation to form regions in the memory and LV areas of the substrate having a second conductivity type different than the first conductivity type; and
performing a second implantation to form regions in the HV area of the substrate having a second conductivity type different than the first conductivity type.
3. The method of claim 2 , wherein an implant energy of the second implantation is greater than an implant energy of the first implantation.
4. The method of claim 2 , further comprising:
forming photo resist over the substrate in the memory area and the LV area before the second implantation, wherein the photo resist blocks the second implantation from the memory area and the LV area.
5. The method of claim 2 , wherein the regions of second conductivity type in the memory and LV areas have a lower breakdown voltage than a breakdown voltage of the regions of second conductivity type in the HV area.
6. The method of claim 1 , wherein the performing of the etch to thin the first conductive layer includes a chemical-mechanical polish etch.