Vertical NROM and methods for making thereof
View Patent ↗Vertical NROM devices are made in a substantially single crystalline silicon substrate having a planar surface. The vertical NROM cell and device has a first region and a second region spaced apart from one another by a channel. A dielectric is spaced apart from the channel to capture charges injected from the channel onto the dielectric. A gate is positioned over the dielectric and spaced apart therefrom and controls the flow of current through the channel. In the improvement of the present invention, a portion of the channel is substantially perpendicular to the top planar surface of the substrate. Methods for making the vertical NROM cell and array are also disclosed.
1. A non-volatile memory device comprising:
a substantially single crystalline semiconductive material of a first conductivity type having a planar surface;
a first region of a second conductivity type, different from said first conductivity type in said material;
a second region of said second conductivity type in said material;
a channel region connecting said first and second regions for the conduction of charges;
a dielectric spaced part from said channel region for trapping charges;
a gate electrode, spaced apart from said dielectric for controlling the conduction of charges in said channel region; and
wherein said channel region has a portion which is substantially perpendicular to said planar surface.
2. The device of claim 1 wherein said channel region is in a trench, said trench having a top portion and a bottom portion.
3. The device of claim 2 wherein said first region is adjacent said top portion.
4. The device of claim 3 wherein said second region is adjacent said bottom portion.
5. The device of claim 2 wherein said top portion has two sides and said first region is adjacent a first side and said second region is adjacent a second side.
6. The device of claim 2 wherein said trench has a side wall connecting said top portion and said bottom portion, and said channel region is along said sidewall, and said gate electrode is in said trench.
7. The device of claim 6 wherein said dielectric is silicon nitride.
8. The device of claim 7 wherein said dielectric is spaced apart from said channel region by a layer of silicon dioxide.
9. The device of claim 8 wherein said gate electrode is spaced apart from said dielectric by a layer of silicon dioxide.
10. A non-volatile memory array comprising:
a substantially single crystalline semiconductive material of a first conductivity type having a planar surface;
a plurality of memory cells in said material, each memory cell comprising:
a first region of a second conductivity type different from said first conductivity type in said material;
a second region of said second conductivity type in said material;
a channel region connecting said first and second regions for the conduction of charges;
a dielectric spaced apart from said channel region for trapping charges;
a gate electrode spaced apart from said dielectric for controlling the conduction of charges in said channel region;
said channel region having a portion which is substantially perpendicular to said planar surface; and
wherein adjacent memory cells have a common first region.
11. The array of claim 10 wherein each of said memory cells has a trench with a top portion and a bottom portion with said channel region in said trench.
12. The array of claim 11 wherein said first region is adjacent said top portion.
13. The array of claim 12 wherein said second region is adjacent said bottom portion.
14. The array of claim 11 wherein said top portion has two sides and said first region is adjacent a first side and said second region is adjacent a second side.
15. The array of claim 11 wherein said trench has a side wall connecting said top portion and said bottom portion, and said channel region is along said sidewall, and said gate electrode is in said trench.
16. The array of claim 15 wherein said dielectric is silicon nitride.
17. The array of claim 16 wherein said dielectric is spaced apart from said channel region by a layer of silicon dioxide.
18. The array of claim 17 wherein said gate electrode is spaced apart from said dielectric by a layer of silicon dioxide.
19. The array of claim 10 wherein said material is recrystallized polysilicon.
20. The array of claim 10 wherein said material is single crystalline silicon.
21. The array of claim 10 wherein said gate electrode of memory cells in a first direction are electrically connected.
22. The array of claim 21 wherein said first region of memory cells in a second direction, substantially perpendicular to the first direction, are electrically connected.
23. The array of claim 22 wherein said second region of memory cells in said second direction are electrically connected.