Programmable serial interface for a semiconductor circuit
View Patent ↗A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.
1. A smart card programmable serial interface for use in a semiconductor circuit that supports a plurality of protocols, the serial interface comprising:
an input/output buffer for use in a smart card and for providing serial communication between the semiconductor circuit and an external device using at least one of the plurality of protocols, the input/output buffer including an electrical connection for coupling to said external device, the input/output buffer being configurable to provide, on the electrical connection, signals having electrical characteristics of each protocol of the plurality of protocols;
at least one shared hardware element for use in the smart card and coupled to the input/output buffer, the shared hardware element performing a common task for said plurality of protocols; and
a programmable logic array for use in the smart card and coupled to the input/output buffer, the programmable logic array implementing one or more additional tasks for said plurality of protocols;
wherein said smart card programmable serial interface is reconfigurable by software to support each protocol of said plurality of protocols.
2. The programmable serial interface of claim 1 , wherein said programmable logic array is reconfigurable.
3. The programmable serial interface of claim 1 , wherein said at least one shared hardware element is reconfigurable.
4. The programmable serial interface of claim 1 , wherein said common task is a serial-to-parallel conversion.
5. The programmable serial interface of claim 1 , wherein said common task is a parallel-to-serial conversion.
6. The programmable serial interface of claim 1 , wherein the semiconductor circuit comprises integrated circuitry logically arranged to implement hardware components that are one or both of shared by the plurality of protocols and/or required for protocol-specific functionality.
7. The programmable serial interface of claim 1 , wherein said common task is a clock recovery function.
8. The programmable serial interface of claim 1 , wherein said additional task is a bit stuffing function.
9. The programmable serial interface of claim 1 , wherein said programmable logic array is a field programmable gate array.
10. The programmable serial interface of claim 1 , wherein said programmable logic array is an electrical programmable logic device (EPLD).
11. A method for designing a smart card semiconductor circuit, said method comprising the steps of:
in a semiconductor circuit for use in a smart card, identifying a plurality of communication protocols to be supported by said semiconductor circuit;
analyzing functions required by each of said supported communication protocols to identify those functions suitable for an implementation using shared hardware with other communication protocols;
designing an input/output buffer for use in a smart card for providing serial communication between the semiconductor circuit and an external device using at least one of the plurality of protocols, the input/output buffer including an electrical connection for coupling to said external device, the input/output buffer being configurable to provide, on the electrical connection, signals having electrical characteristics of each protocol of the plurality of protocols; and
designing a shared hardware element for use in the smart card and coupled to the input/output buffer, the shared hardware element performing a common task for said plurality of communication protocols;
wherein said semiconductor circuit is reconfigurable by software to support each protocol of said plurality of communication protocols.
12. The method of claim 11 , further comprising the step of identifying functions required by a supported communication protocol that must be performed in hardware.
13. The method of claim 12 , wherein said hardware is a programmable logic array.
14. The method of claim 13 , wherein said programmable logic array is reconfigurable.
15. The method of claim 13 , wherein said programmable logic array is a field programmable gate array.
16. The method of claim 13 , wherein said programmable logic array is an electrical programmable logic device (EPLD).
17. The method of claim 11 , further comprising the step of implementing at least a portion of the functions required by a supported communication protocol in software.
18. The method of claim 11 , wherein said shared hardware element is reconfigurable.
19. A system for designing a smart card semiconductor circuit, said system comprising:
a memory that stores computer-readable code; and
a processor operatively coupled to said memory, said processor configured to implement said computer-readable code, said computer-readable code configured to:
identify a plurality of communication protocols to be supported by said semiconductor circuit;
analyze functions required by each of said supported communication protocols to identify those functions suitable for an implementation using shared hardware with other communication protocols;
design an input/output buffer for use in a smart card for providing serial communication between the semiconductor circuit and an external device using at least one of the plurality of protocols, the input/output buffer including an electrical connection for coupling to said external device, the input/output buffer being configurable to provide, on the electrical connection, signals having electrical characteristics of each protocol of the plurality of protocols; and
design a shared hardware element for use in the smart card and coupled to the input/output buffer, the shared hardware element performing a common task for said plurality of communication protocols;
wherein said smart card semiconductor circuit is reconfigurable by software to support each protocol of said plurality of communication protocols.
20. The system of claim 19 , wherein said processor is further configured to identify functions required by a supported communication protocol that must be performed in hardware.
21. The system of claim 19 , wherein said processor is further configured to identify functions required by a supported communication protocol to be performed in software.