Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure
View Patent ↗A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
1. A stack gate structure for use in a non-volatile memory array comprising:
a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction;
a plurality of stack gate structures, each stack gate structure over an active region, with a first insulating material between each stack gate structure in a second direction perpendicular to the first direction; each stack gate structure comprising:
a second insulating material over the active region;
a charge holding gate over the second insulating material;
a third insulating material over the charge holding gate;
a first portion of a control gate over the third insulating material;
a second portion of the control gate over the top surface of the first portion of the control gate and over the top surface of the first insulating material adjacent thereto extending in the second direction; and
a fourth insulating material over the second portion of the control gate;
wherein said first portion of the control gate is polysilicon and has a top surface that is substantially co-planar with the top surface of the first insulating material adjacent thereto; and
a plurality of isolation regions in the semiconductor substrate, with each isolation region between a pair of the active regions, wherein each isolation region comprises:
a trench formed into the substrate, wherein one of the first insulating material extends down into and fills the trench.
2. The stack gate structure of claim 1 wherein said first insulating material is silicon oxide.
3. The stack gate structure of claim 2 wherein said second insulating material is silicon dioxide.
4. The stack gate structure of claim 1 , wherein said charge holding gate is a floating gate.
5. The stack gate structure of claim 4 wherein said floating gate is made of polysilicon.
6. The stack gate structure of claim 1 wherein said charge holding gate is a charge trapping layer.
7. The stack gate structure of claim 6 wherein said charge trapping layer is silicon nitride.
8. The stack gate structure of claim 1 wherein said third insulating material is a composite insulator of silicon dioxide, silicon nitride, and silicon dioxide.
9. The stack gate structure of claim 1 wherein said second portion of the control gate is polysilicon.
10. The stack gate structure of claim 1 wherein said fourth insulating material is a composite insulating layer of silicon nitride, silicon dioxide and silicon nitride.