Differential sense amplifier for multilevel non-volatile memory
View Patent ↗A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
1. A differential sense amplifier for a non-volatile memory, comprising:
a preamplifier stage providing first and second preamp output signals in response to first and second input signals; and
a latch analog bootstrap amplifier stage coupled to the preamplifier stage to latch the first and second preamp output signals, and, in response thereto, provide first and second amplifier output signals.
2. The differential sense amplifier of claim 1 wherein the preamplifier stage comprises a latch.
3. The differential sense amplifier of claim 1 wherein the preamplifier stage comprises a latch including an initial latching amplification circuit.
4. The differential sense amplifier of claim 3 wherein the initial amplification circuit includes an analog bootstrap circuit.
5. The differential sense amplifier of claim 2 wherein the latch analog bootstrap amplifier stage comprises a first capacitor coupled between the first preamp output signal and the first amplifier output signal and a second capacitor coupled between the second preamp output signal and the second amplifier output signal.
6. The differential sense amplifier of claim 1 wherein the preamplifier stage including a gain enhancement circuit.
7. The differential sense amplifier of claim 1 wherein the latch analog bootstrap amplifier stage includes a gain enhancement circuit for post amplification.
8. A differential sense amplifier for a non-volatile memory, comprising:
a preamplifier stage generating first and second output voltages in response to first and second input voltages; and
an amplifier stage coupled to the preamplifier stage to generate a third output voltage in response to the first output voltage being greater than the second output voltage and generating a fourth output voltage in response to the first output voltage being less than the second output voltage, the amplifier stage comprising:
a first transistor of a first type including a first terminal coupled to the third output voltage, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to the first output voltage;
a second transistor of the first type including a first terminal coupled to the fourth output voltage, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second terminal of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to the second output voltage;
a third transistor of the first type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel in response to a first control signal;
a first transistor of a second type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the first terminal of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to the first terminal of the second transistor of the first type; and
a second transistor of the second type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the first terminal of the second transistor of the first type, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the first type.
9. The differential sense amplifier of claim 8 further comprising a gain enhancement circuit for pulling down the third and fourth output voltage in response to the second and first output voltage being in a low state.
10. The differential sense amplifier of claim 8 further comprising:
a fourth transistor of the first type including a first terminal coupled to the first terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to the first terminal of the second transistor of the first type;
a fifth transistor of the first type including a first terminal coupled to the first terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second of the fourth transistor of the first type and including a gate for controlling current in said channel and coupled to the first terminal of the fourth transistor of the first type; and
a sixth transistor of the first type including a first terminal coupled to the second terminal of the fourth transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel in response to a second control signal.
11. The differential sense amplifier of claim 10 further comprising:
a first capacitor coupled between the gate of the first transistor of the second type and the first output voltage; and
a second capacitor coupled between the gate of the second transistor of the second type and the second output voltage.
12. The differential sense amplifier of claim 11 further comprising an equalization circuit for equalizing the voltage of the third and fourth output voltages prior to application of the first and second input voltages.
13. The differential sense amplifier of claim 12 wherein the second control signal is applied after the equalization of the equalization circuit.
14. A differential sense amplifier for a non-volatile memory, comprising:
a preamplifier stage generating first and second output voltages in response to first and second input voltages, the preamplifier stage including a folded cascode amplifier and a gain enhancement circuit; and
an amplifier stage coupled to the preamplifier stage to generate a third output voltage in response to the first output voltage being greater than the second output voltage and generating a fourth output voltage in response to the first output voltage being less than the second output voltage.
15. The differential sense amplifier of claim 14 wherein the gain enhancement circuit comprises:
a first transistor of a first type including a first terminal coupled to the second output voltage, including a second terminal spaced apart from first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel and coupled to the first output voltage; and
a second transistor of the first type including a first terminal coupled to the first output voltage, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the second output voltage.
16. The differential sense amplifier of claim 14 wherein the prestage amplifier comprises:
a first transistor of a first type including a first terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel in response to the first input voltage;
a second transistor of the first type including a first terminal, including a second terminal spaced apart from said first terminal and coupled to the second terminal of the first transistor of the first type, and including a gate for controlling current in said channel in response to the second input voltage;
a third transistor of the first type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling a current in said channel in response to a first control signal;
a first transistor of a second type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the first terminal of the first transistor of the first type, and including a gate for controlling current in said channel;
a second transistor of the second type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the first terminal of the second transistor of the first type, and including a gate for controlling current in said channel and coupled to the gate of the first transistor of the second type;
a third transistor of the second type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the second type, and including a gate for controlling current in said channel and coupled to the second terminal of the third transistor of the second type;
a fourth transistor of the first type including a first terminal coupled to the second terminal of the third transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel in response to the first control signal;
a fourth transistor of the second type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to said second terminal;
a fifth transistor of the first type including a first terminal coupled to the second terminal of the fourth transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel in response to the first control signal;
a fifth transistor of the second type including a first terminal coupled to the second terminal of the first transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second output voltage, and including a gate for controlling current in said channel and coupled to the second terminal of the fourth transistor of the second type;
a sixth transistor of the first type including a first terminal coupled to the second terminal of the fifth transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the second terminal of the fifth transistor of the second type;
a sixth transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the first output voltage, and including a gate for controlling current in said channel and coupled to the second terminal of the fourth transistor of the second type; and
a seventh transistor of the first type including a first terminal coupled to the second terminal of the sixth transistor of the second type, including a second terminal spaced apart form said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal.
17. The differential sense amplifier of claim 16 further comprising:
an eighth transistor of the first type including a first terminal coupled to the first terminal of the seventh transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, including the gate for controlling current in said channel and coupled to the first terminal of the sixth transistor of the first type; and
a ninth transistor of the first type including a first terminal coupled to the first terminal of the sixth transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the first terminal of the seventh transistor of the first type.
18. The differential sense amplifier of claim 14 wherein the preamplifier stage further comprises a clamp circuit to equalize internal voltages of the folded cascode amplifier.
19. The differential sense amplifier of claim 14 wherein the folded cascode amplifier generates first and second internal voltages in response to the first and second input voltages and generates said first and second output voltages in response to the first and second internal voltages, and
the folded cascode amplifier further comprises:
a first transistor of a first type including a first terminal coupled to the first internal voltage, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to said second internal voltage, and including a gate for controlling current in said channel and coupled to said second terminal, and
a second transistor of the first type including a first terminal coupled to the first internal voltage, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to said second internal voltage, and including a gate for controlling the current in said channel and coupled to said first terminal.
20. The differential sense amplifier of claim 14 wherein the amplifier stage includes an analog bootstrap circuit.
21. The differential sense amplifier of claim 20 wherein the analog bootstrap circuit comprises a first capacitor coupled between the first output voltage and the third output voltage, and further comprises a second capacitor coupled between the second output voltage and the fourth output voltage.
22. The differential sense amplifier of claim 14 wherein the amplifier stage comprises a gain enhancement circuit for pulling down the third and fourth output voltages in response to the second and first output voltages being in a low state.
23. The differential sense amplifier of claim 22 wherein the post amplification circuit comprises:
a first transistor of a first type including a first terminal coupled to the third output voltage, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to the fourth output voltage,
a second transistor of the first type including a first terminal coupled to the fourth output voltage, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second terminal of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to the third output voltage, and
a third transistor of the first type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel in response to a control signal.