User identification for multi-purpose flash memory
View Patent ↗A memory system includes manufacturer identifiers, such as serial numbers and part numbers, stored in locations of memory that are unalterable by end users. A customer identification location of the memory allows the user to program its own identifier and includes a locking code that prevents subsequent alteration of the customer identification location. A recall procedure at power on verifies the content of the locked code for allowing alteration of the memory.
1. A memory system comprising:
a memory including a first storage area for storing a user selected identifier and a second storage area for storing a locking code;
a recall circuit for reading said second storage area in response to a power-on reset signal;
a control circuit for prohibiting alteration of the contents in the first storage area in the event the locking code is in a first state and for allowing alteration of the contents in the first storage area in the event the locking code is in a second state.
2. The memory system of claim 1 wherein the second storage area is unalterable in the event the locking code is in said first state.
3. The memory system of claim 1 further comprising a high voltage generator for generating a program voltage signal and an erase voltage signal to program or erase contents in selected portions of the memory, the high voltage generator not providing said program voltage signal or said erase voltage signal to said first storage area in the event the control circuit prohibits alteration of the contents in the first storage area.
4. The memory system of claim 1 wherein the first and second storage areas are on the same word line.
5. The memory system of claim 4 wherein the control circuit includes a pointer to the second word line that points to the second word line and the locking code is not set to prevent writing.
6. A memory system comprising:
a memory including a first storage area for storing a user selected identifier;
a recall circuit for reading said first storage area in response to a power-on reset signal;
a high voltage generator for generating a program voltage signal and an erase voltage signal to program or erase contents in selected portions of the memory, the high voltage generator not providing said program voltage signal or said erase voltage signal to said first storage area in the event the recall circuit does not read the first storage area and providing said program voltage signal and said erase voltage signal to said first storage area in the event that the recall circuit reads the first storage area.
7. A method for storing data in a memory, the method comprising:
storing a user selected identifier in a first storage area;
storing a locking code in a second storage area of the memory;
reading said second storage area in response to a power-on reset signal;
prohibiting alteration of the contents in the first storage area in the event the locking code is in a first state and allowing alteration of the contents in the first storage area in the event the locking code is in a second state.
8. The method of claim 7 wherein the second storage area is unalterable in the event the locking code is in said first state.
9. The method of claim 7 further comprising:
generating a program voltage signal and an erase voltage signal to program or erase contents in selected portions of the memory in the event the locking code is in said second state; and
prohibiting application of the program voltage signal and the erase voltage signal to the memory in the event the locking code is in the first state.
10. A method comprising:
reading a first storage area in a memory cell to validate whether a user selected identifier is stored in said first storage area after receipt of a power-on reset signal;
generating a high voltage signal to alter the contents in selected portions of the memory in the event the read user selected identifier is not read from the first storage area.
11. A memory system comprising:
a memory including a first storage area for storing a user selected identifier and a second storage area for storing a locking code;
an input interface for receiving a command signal;
a control circuit generating a first write signal to control a write to the first storage area to store the user selected identifier in response to the command signal being a program command and the locking code being in a first state, generating a read signal to control a read of the first storage area in response to the command signal being a read command, and generating a second write signal to control a write to the first storage area to store the user selected identifier and to control a write to the second storage area of a locking code in a second state in the response to the command signal being a program and lock command and the locking code stored in the second storage area being in the first state.
12. The memory system of claim 11 further comprising a high voltage generator for generating a program voltage signal and an erase voltage signal to program or erase contents in selected portions of the memory, the high voltage generator not providing program voltage signal or said erase voltage signal to said first storage area in the event the control circuit prohibits alteration of the contents in the first storage area.
13. A method comprising:
receiving a command signal;
generating a first write signal to control a write to a first storage area of a memory to store a user selected identifier in response to the command signal being a program command and a locking code stored in a second storage area of the memory being in a first state;
generating a read signal to control a read of the first storage area in response to the command signal being a read command, and
generating a second write signal to control a write to the first storage area to store the user selected identifier and to control a write to the second storage area of a locking code in a second state in the response to the command signal being a program and lock command and the locking code stored in the second storage area being in the first state.
14. The method of claim 13 further comprising:
generating a program voltage signal and an erase voltage signal to program or erase contents in selected portions of the memory; and
blocking the application of the program voltage signal and the erase voltage signal to said first storage area in the event the locking code stored in the second storage area is in the second state.