Charge pump systems and methods
View Patent ↗Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
1. The charge pump comprising:
a plurality of pump stages arranged in successive stages, including stage N and a plurality of stages prior to N, each pump stage of the plurality of pump stages including an output node, a first node, a first transistor coupled between an input node and the first node, and a second transistor coupled between the output node and the first node;
wherein the second transistor of stage N is coupled to a different stage, before or after stage N, of the pump stages arranged in successive stages to acquire a reference voltage used to discharge the first node;
wherein each pump stage has a precharge circuit associated therewith; and
wherein at least one of the precharge circuits of stage N or a stage after stage N includes a third transistor and a fourth transistor, with a gate of the third transistor or the fourth transistor being coupled to a second node of another pump stage of the pump stages arranged in successive stages to provide self-biased buffering to prevent high voltage breakdown of a transistor in the precharge circuit.
2. The charge pump of claim 1 , wherein the second transistor is coupled to the first node of the different stage.
3. The charge pump of claim 1 , wherein a gate of the second transistor is coupled to the first node of the different stage.
4. The charge pump of claim 1 , wherein, in each pump stage, a gate of the first transistor and a source or drain of the second transistor are coupled to a reference node.
5. The charge pump of claim 1 , wherein the second transistor is an NMOS transistor.
6. The charge pump of claim 1 , wherein the second transistor is a native NMOS transistor.
7. The charge pump of claim 1 , wherein the different stage is one stage earlier than stage N.
8. The charge pump of claim 1 , wherein the different stage is two stages earlier than stage N.
9. The charge pump of claim 7 , wherein the second transistor is coupled to a reference node of the different stage.
10. The charge pump of claim 7 , wherein a gate of the second transistor is coupled to a reference node of the different stage.
11. The charge pump of claim 7 , wherein, in each pump stage, a gate of the first transistor and a source or drain of the second transistor are coupled to a reference node.
12. The charge pump of claim 7 , wherein the second transistor is an NMOS transistor.
13. The charge pump of claim 7 , wherein the second transistor is a native NMOS transistor.
14. The charge pump of claim 1 , wherein the second node of the another stage is the input node or the output node of the another stage.
15. The charge pump of claim 1 , wherein the third transistor and the fourth transistor are coupled in series.
16. The charge pump of claim 1 , wherein the another pump stage is one stage earlier than stage N.
17. The charge pump of claim 1 , wherein the another pump stage is two stages earlier than stage N.
18. The charge pump of claim 14 , wherein the second transistor is coupled to the first node of the different stage.
19. The charge pump of claim 16 , wherein a gate of the second transistor is coupled to the first node of the different stage.
20. The charge pump of claim 16 , wherein, in each pump stage, a gate of the first transistor and a source or drain of the second transistor are coupled to a reference node.