Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation
View Patent ↗A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.
1. A method of manufacturing an array of non-volatile memory cells in a substantially single crystalline semiconductive substrate of a first conductivity type, wherein said array of non-volatile memory cells has a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said semiconductive substrate with each cell for storing a plurality of bits, said method comprising:
forming spaced apart isolation regions on said semiconductive substrate that are substantially parallel to one another and extend in a said column direction, with an active region between each pair of adjacent isolation regions, wherein said semiconducive substrate has a surface;
forming a plurality of memory cells in each of the active regions, wherein each memory cell for the storage of a plurality of bits, wherein the formation of each of the memory cells includes:
forming a first and a second spaced apart trenches into the surface of the substrate, each of said first and second trenches having a sidewall and a bottom wall;
forming a first region and a second region in said bottom wall of said first and second trenches, respectively, with said first region and said second region being of a second conductivity type, different from said first conductivity type, with a channel region for the conduction of charges connecting said first region and said second region; said channel region, having a first portion, a second portion and a third portion;
forming a dielectric on said channel region;
forming a first floating gate on said dielectric, in said first trench spaced apart from said sidewall of said first trench and from said first portion of said channel region; said first portion of said channel region adjacent to said first region, said first floating gate for the storage of at least one of said plurality of bits;
forming a second floating gate on said dielectric, in said second trench spaced apart from said sidewall of said second trench and from said second portion of said channel region; said second portion of said channel region adjacent to said second region, said second floating gate for the storage of at least another of said plurality of bits;
forming a gate electrode on said dielectric, spaced apart from said third portion of said channel region, said third portion of said channel region between said first portion and said second portion;
forming a first gate electrode in said first trench, said first gate electrode electrically connected to said first region and capacitively coupled to said first floating gate; and
forming a second gate electrode in said second trench, said second gate electrode electrically connected to said second region and capacitively coupled to said second floating gate.
2. The method of claim 1 wherein said step of forming said first gate electrode includes forming said first gate electrode continuously in said row direction across a plurality of columns.
3. The method of claim 2 wherein said step of forming said second gate electrode includes forming said second gate electrode continuously in said row direction across a plurality of columns.
4. The method of claim 3 wherein said step of forming said first region and said second region includes forming said first region and said second region continuously in said row direction across a plurality of columns.
5. The method of claim 3 wherein said step of forming said first region and said second region includes forming said first region and said second region in only one column of active region.
6. The method of claim 3 wherein said step of forming said gate electrode includes forming said gate electrode continuously in said column direction across a plurality of memory cells.
7. A method of manufacturing a non-volatile memory cell in a substantially single crystalline semiconductive substrate of a first conductivity type, wherein said non-volatile memory cell for storing a plurality of bits, said method comprising:
forming a first and a second spaced apart trenches into the surface of the substrate, each of said first and second trenches having a sidewall and a bottom wall;
forming a first region and a second region in said bottom wall of said first and second trenches, respectively, with said first region and said second region being of a second conductivity type, different from said first conductivity type, with a channel region for the conduction of charges connecting said first region and said second region; said channel region, having a first portion, a second portion and a third portion;
forming a dielectric on said channel region;
forming a first floating gate an said dielectric, in said first trench spaced apart from said sidewall of said first trench and from said first portion of said channel region; said first portion of said channel region adjacent to said first region, said first floating gate for the storage of at least one of said plurality of bits;
forming a second floating gate on said dielectric, in said second trench spaced apart from said sidewall of said second trench and from said second portion of said channel region; said second portion of said channel region adjacent to said second region, said second floating gate for the storage of at least another of said plurality of bits;
forming a gate electrode on said dielectric, spaced apart from said third portion of said channel region, said third portion of said channel region between said first portion and said second portion;
forming a first gate electrode in said first trench, said first gate electrode electrically connected to said first region and capacitively coupled to said first floating gate; and
forming a second gate electrode in said second trench, said second gate electrode electrically connected to said second region and capacitively coupled to said second floating gate.
8. The method of claim 7 wherein said step of forming a gate electrode on said dielectric further includes forming an insulation material between the gate electrode and said first and second floating gates with a thickness that permits Fowler-Nordheim tunneling of electrons from said first and second floating gates to said gate electrode.
9. The method of claim 8 wherein said step of forming said first and second floating gates includes forming said first and second floating gates above the substrate surface.