Granted Patent B2

US 6,853,584 · App. 10/428,742 · Granted Feb 8, 2005

Abstract

Claims (34)

1. A semiconductor memory device comprising:

a memory array having a plurality of rows and columns for receiving a plurality of first signals, said plurality of first signals affecting the total amount of current flowing through a first group of said columns;

a voltage source having an output;

a conducting path connecting said output to said first group of said columns;

a transistor in said conducting path, for controlling the current flow in said conducting path; said transistor having a control terminal;

a current source having a first terminal and a second terminal, with said first terminal connected to said output, and said second terminal connected to said control terminal;

a first plurality of current sources collectively connected to a node; said first plurality of current sources for receiving a plurality of second signals, each of said second signal being an inverse of said first signal, said plurality of second signals affecting the total amount of current flowing through said first plurality of current sources at said node; and

a current mirror circuit having a first branch connected to said node, and a second branch mirroring current flowing in said first branch, with said second branch connected to said control terminal.

2. The device of claim 1 wherein said current mirror circuit comprises:

said first branch comprising:

a first PMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the conduction of charges in said channel; said first terminal connected to a first voltage source, said second terminal connected to said gate and to said node;

said second branch comprising:

a second PMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the conduction of charges in said channel; said first terminal connected to said first voltage source, said gate connected to said gate of said first PMOS transistor;

a first NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the conduction of charges in said channel; said first terminal connected to said gate of said first NMOS transistor and to said second terminal of said second PMOS transistor, said second terminal connected to ground;

a second NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the conduction of charges in said channel; said gate of said second NMOS transistor connected to said gate of said first NMOS transistor; said first terminal of said second NMOS transistor connected to said control terminal and said second terminal of said second NMOS transistor connected to ground.

3. The device of claim 1 wherein said memory array comprises an array of floating gate non-volatile memory cells.

4. The device of claim 3 wherein said array of memory cells are arranged in an array accessed by said plurality of rows and columns.

5. The device of claim 4 wherein each memory cell of said memory array is a split gate floating gate non-volatile memory cell.

6. The device of claim 4 wherein each memory cell of said memory array is a stacked gate floating gate non-volatile memory cell.

7. A semiconductor memory device comprising:

an array of memory cells arranged in a plurality of rows and columns; each cell for storing at least two states: a first state and a second state, wherein the current flow supplied to a memory cell differs for said memory cell storing said first state from said memory cell storing said second state;

a plurality of rows and columns for accessing said array of memory cells, wherein said columns provide current to said array for storing one of said at least two states;

said array of memory cells for receiving a plurality of first signals affecting the total amount of current flowing through a first group of columns in said plurality of columns;

a voltage source having an output;

a conducting path connecting said output to said first group of columns;

a current controller in said conducting path for controlling current flow in said conducting path, said controller having a control terminal;

a first current source having a first terminal and a second terminal, with said first terminal connected to said output and said second terminal connected to said control terminal;

a second current source connected to a node; said second current source controlled by a plurality of second signals, wherein each second signal is an inverse of a first signal, and wherein said plurality of second signals affect the total amount of current flowing through said second current source at said node; and

a current mirror circuit having a first terminal and a second terminal, with said first terminal connected to said node and with said second terminal connected to said control terminal, wherein the amount of current flowing through said first terminal is mirrored by the amount of current flowing through said second terminal.

8. The device of claim 7 wherein each of said memory cells is a floating gate non-volatile memory cell.

9. The device of claim 8 wherein each of said memory cells is a split gate floating gate non-volatile memory cell.

10. The device of claim 8 wherein each of said memory cells is a stacked gate floating gate non-volatile memory cell.

11. The device of claim 7 wherein said second current source comprises a plurality of current sources, each controlled by a second signal.

12. The device of claim 7 wherein said current controller is a transistor having a first terminal, a second terminal with a channel therebetween, and a gate for controlling the flow of charges in said channel, said first terminal connected to said output, said second terminal connected to said first group of columns, and said gate being said control terminal.

Assignments (15)