IP Library Granted Patent US 10,658,027
Granted Patent B2
US 10,658,027 · App. 15/002,302 · Granted May 19, 2020

High density split-gate memory cell

Inventors: Nhan Do (Saratoga, CA); Xian Liu (Sunnyvale, CA); Vipin Tiwari (Dublin, CA); Hieu Van Tran (San Jose, CA)
Assignee: Silicon Storage Technology, Inc.
G11C11/419G11C16/0458G11C16/14H01L27/11521H01L29/40114H01L29/42328H01L29/66825H01L29/7887
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Quick Facts
Patent No.
US 10,658,027
App. No.
15/002,302
Granted
May 19, 2020
Kind
B2
Abstract

A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

Claims (40)

1. A method of forming a memory device, comprising:

forming a plurality of separated first trenches into a surface of a semiconductor substrate, wherein the first trenches are parallel to each other and extend in a first direction and define active regions of the substrate between the first trenches;

filling the first trenches with insulation material;

forming a first insulation layer on the surface of the substrate in each of the active regions;

forming a first conductive layer on the first insulation layer in each of the active regions;

forming a second insulation layer on the first conductive layer in each of the active regions;

forming a second conductive layer on the second insulation layer in each of the active regions;

forming a third insulation layer on the second conductive layer in each of the active regions;

forming a plurality of separated second trenches through the third insulation layer, wherein the second trenches are parallel to each other and extend in a second direction perpendicular to the first direction;

extending the second trenches through the second conductive layer and the second insulation layer;

extending the second trenches through the first conductive layer, leaving side portions of the first conductive layer exposed and leaving the first insulation layer on the surface of the substrate at the bottom of the second trenches;

forming a fourth insulation layer vertically and directly on the first insulation layer at the bottom of the second trenches and along the exposed portions of the first conductive layer, wherein the fourth insulation layer is not in direct contact with the substrate;

filling the second trenches with conductive material, wherein the conductive material is insulated from the first conductive layer by the fourth insulation layer and from the substrate surface in a vertical direction by the first insulation layer and the fourth insulation layer;

forming a plurality of third trenches through the third insulation layer, wherein the third trenches are parallel to each other and extend in the second direction such that the second and third trenches alternate each other;

extending the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer;

performing an implantation to form drain regions in the substrate under the third trenches.

2. The method of claim 1 , further comprising:

forming spacers of insulation material along sidewalls of the second trenches after the extending of the second trenches through the second conductive layer and the second insulation layer, and before the extending of the second trenches through the first conductive layer.

3. The method of claim 1 , further comprising:

forming spacers of insulation material along sidewalls of the third trenches after the extending of the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer.

4. The method of claim 1 , wherein the first and second conductive layers are polysilicon.

5. The method of claim 1 , wherein the first insulation layer is oxide.

6. The method of claim 1 , wherein the second insulation layer is an ONO insulation layer comprising oxide, nitride, and oxide sublayers.

7. A method of forming a memory device, comprising:

forming a plurality of separated first trenches into a surface of a semiconductor substrate, wherein the first trenches are parallel to each other and extend in a first direction and define active regions of the substrate between the first trenches;

filling the first trenches with insulation material;

forming a first insulation layer on the surface of the substrate in each of the active regions;

forming a first conductive layer on the first insulation layer in each of the active regions;

forming a second insulation layer on the first conductive layer in each of the active regions;

forming a second conductive layer on the second insulation layer in each of the active regions;

forming a third insulation layer on the second conductive layer in each of the active regions;

forming a plurality of separated second trenches through the third insulation layer, wherein the second trenches are parallel to each other and extend in a second direction perpendicular to the first direction;

extending the second trenches through the second conductive layer and the second insulation layer;

extending the second trenches through the first conductive layer, leaving side portions of the first conductive layer exposed and leaving the first insulation layer on the surface of the substrate at the bottom of the second trenches;

forming a fourth insulation layer vertically on the first insulation layer at the bottom of the second trenches and along the exposed portions of the first conductive layer, wherein the fourth insulation layer is not in direct contact with the substrate;

filling the second trenches with conductive material, wherein the conductive material is insulated from the first conductive layer by the fourth insulation layer and from the substrate surface in a vertical direction by the first insulation layer and the fourth insulation layer;

forming a plurality of third trenches through the third insulation layer, wherein the third trenches are parallel to each other and extend in the second direction such that the second and third trenches alternate each other;

extending the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer;

performing an implantation to form drain regions in the substrate under the third trenches;

wherein the extending of the third trenches further includes extending the third trenches through the first insulation layer.

Assignments (19)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 059687/0344 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: SILICON STORAGE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0316 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2016
From: DO, NHAN; LIU, XIAN; TIWARI, VIPIN; TRAN, HIEU VAN
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 038431/0102 →