Granted Patent B2

US 9,767,911 · App. 14/791,213 · Granted Sep 19, 2017

Abstract

Claims (10)

1. A programming circuit for use in a memory device, comprising:

a current mirror comprising a transistor, the transistor comprising a first terminal, a second terminal, and a gate;

a memory cell replica coupled to the first terminal of the transistor;

a capacitor coupled to the gate of the transistor;

a switch coupled to a current source, wherein:

in a first mode, the current source is coupled to the gate of the transistor, the capacitor, and the memory cell replica through a closing of the switch, and

in a second mode, the current source is uncoupled from the gate of the transistor, the capacitor, and the memory cell replica, wherein the capacitor applies a bias voltage to the gate of the transistor and the transistor programs a selected memory cell.

2. The circuit of claim 1 , wherein the memory cell replica is a split gate flash memory cell.

3. The programming circuit of claim 1 , wherein the transistor is an enhancement NMOS transistor.

4. The programming circuit of claim 2 , wherein the transistor is an enhancement NMOS transistor.

Assignments (14)