Low power operation for flash memory system
View Patent ↗The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.
1. A non-volatile memory device comprising:
a first circuit capable of operating in a shut down mode, wherein during shut down mode:
a power source for the first circuit is shut down;
a first node in the first circuit is selectively connected to a second circuit that drives the first node to a high level and maintains the high level after the power source for the first circuit is shut down; and
a second node in the first circuit is selectively connected to a third circuit that drives the second node to a low level and maintains the low level after the power source for the first circuit is shut down.
2. The memory device of claim 1 , wherein the first circuit is a decoder circuit.
3. The memory device of claim 1 , wherein the first circuit is a test mode circuit.
4. The memory device of claim 2 , further comprising a bulk voltage coupled to bulks of one or more transistors in the decoder circuit.
5. The memory device of claim 2 , wherein the decoder circuit comprises a row decoder circuit.
6. The memory device of claim 1 , wherein the first node is selectively connected to the second circuit through a first switch.
7. The memory device of claim 6 , wherein the second node is selectively connected to the third circuit through a second switch.
8. The memory device of claim 1 , wherein a third node in the first circuit is selectively connected to the second circuit that drives the third node to a high level.
9. The memory device of claim 1 , wherein a fourth node in the first circuit is selectively connected to the third circuit that drives the fourth node to a low level.
10. The memory device of claim 8 , wherein a fourth node in the first circuit is selectively connected to the third circuit that drives the fourth node to a low level.
11. The method of claim 1 , wherein the first node and second node hold the same level from shut down mode to active mode.
12. A method of executing a shut down mode in a non-volatile memory device comprising a first circuit, the method comprising:
asserting a signal that indicates the shut down mode;
in response to the signal, shutting down a power source for the first circuit;
selectively connecting a first node in the first circuit to a second circuit that drives the first node to a high level and maintains the high level after the shutting down step; and
selectively connecting a second node in the first circuit to a third circuit that drives the second node to a low level and maintains the low level after the shutting down step.
13. The method of claim 12 , wherein the first circuit is a decoder circuit.
14. The method of claim 12 , wherein the first circuit is a test mode circuit.
15. The method of claim 13 , further comprising coupling a bulk voltage to bulks of one or more transistors in the decoder circuit.
16. The method of claim 13 , wherein the decoder circuit comprises a row decoder circuit.
17. The method of claim 12 , wherein the step of selectively connecting the first node to the second circuit comprises closing a first switch.
18. The method of claim 17 , wherein the step of selectively connecting the second node to the third circuit comprises closing a second switch.
19. The method of claim 12 , further comprising selectively connecting a third node in the first circuit to the second circuit to drive he third node to a high level.
20. The method of claim 12 , further comprising selectively connecting a fourth node in the first circuit to the third circuit to drive the fourth node to a low level.
21. The method of claim 19 , further comprising selectively connecting a fourth node in the first circuit to the third circuit to drive the fourth node to a low level.
22. The method of claim 12 , wherein the first node and second node hold the same level from shut down mode to active mode.
23. A method of executing a shut down mode in a non-volatile memory device comprising a first circuit, the method comprising:
asserting a signal that indicates the shut down mode;
in response to the signal, shutting down a power source for the first circuit;
selectively connecting a first node in the first circuit to a second circuit that drives the first node to a high level and maintains the high level after the shutting down step; and
selectively connecting a second node in the first circuit to a third circuit that drives the second node to a low level and maintains the low level after the shutting down step.
24. A method of executing a shut down mode in a non-volatile memory device comprising a first circuit, the method comprising:
asserting a signal that indicates the shut down mode;
in response to the signal, shutting down a power source for the first circuit;
selectively connecting a first node in the first circuit to a second circuit that drives the first node to a high level; and
selectively connecting a second node in the first circuit to a third circuit that drives the second node to a low level;
wherein the first node and second node hold the same level from shut down mode to active mode;
asserting a shut down mode for circuit blocks comprising an array, row decoder, column decoder, high voltage decoder, sensing block, data out block, testmode block, trimbits-live block, trimbits block, command decoder, data in block, analog low voltage block, analog high voltage block, non-volatile controller, and
not asserting the shut down mode for circuit blocks comprising a power sequence controller, pin interface, and global power switch during a hard power down mode.
25. The method of claim 23 , further comprising:
asserting the shut down mode for circuit blocks comprising part of an array, part of a row decoder, part of a column decoder, part of a high voltage decoder, part of a sensing block, data out block, testmode block, trimbits block, data in block, analog high voltage block, non-volatile controller, and
not asserting the shut down mode for circuit blocks comprising trimbits-live block, command decoder, analog low voltage block, power sequence controller, pin interface, and global power switch in a standby mode.
26. The method of claim 23 , further comprising:
asserting the shut down mode for circuit blocks comprising part of an array, part of a row decoder, part of a column decoder, part of a high voltage decoder, part of a sensing block, testmode block, trimbits block, data in block, analog high voltage block, non-volatile controller, and
not asserting the shut down mode for circuit blocks comprising data out block, trimbits-live block, command decoder, analog low voltage block, power sequence controller, pin interface, and global power switch in the active mode.
27. The method of claim 23 , further comprising:
asserting the shut down mode for circuit blocks comprising part of an array, part of a row decoder, part of a column decoder, part of a high voltage decoder, sensing block, data out block, testmode block, and
not asserting the shut down mode for circuit blocks comprising trimbits-live block, trimbits block, command decoder, data in block, analog low voltage block, analog high voltage block, non-volatile controller, power sequence controller, pin interface, and global power switch in the non-volatile operation mode.