Non-volatile memory element integratable with standard CMOS circuitry
View Patent ↗A non-volatile memory cell and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor element coupled to the antifuse element and configured to provide one or more voltage pulses to the programming node. The antifuse element is configured to have a changed resistivity after the programming node is subjected to the one or more voltage pulses, the change in resistivity representing a change in logic state. The antifuse element comprises a MOS transistor, its gate being coupled to one of the programming node and a control node, and its source and drain being coupled to the other one of the programming node and the control node. The MOS transistor is formed in a well and the source, drain and well are coupled to the same voltage level.
1. A non-volatile memory cell formed in a semiconductor substrate comprising:
an antifuse element having a programming node, the antifuse element being configured to have changed resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state; and
a capacitor element coupled to the antifuse element and configured to provide the one or more voltage pulses to the programming node;
wherein the antifuse element comprises a MOS transistor having a gate, a source, and a drain, the gate being coupled to one of the programming node and a control node and the source and drain being coupled to the other one of the programming node and the control node;
wherein the MOS transistor antifuse element is formed in a well having a first type of conductivity that is opposite to a second type of conductivity from which the substrate is formed and the source and drain of the MOS transistor antifuse element have the first type of conductivity, and wherein the source, drain and well of the MOS transistor antifuse element are configured to be coupled to the same voltage level.
2. The non-volatile memory cell of claim 1 , wherein the first type of conductivity is type n and the second type of conductivity is type p and the MOS transistor antifuse element comprises an NMOS transistor formed in an nwell.
3. The non-volatile memory cell of claim 1 , wherein the MOS transistor antifuse element is formed in the semiconductor substrate so that a channel region of the MOS transistor antifuse element that is under a dielectric layer is not altered by a halo implant.
4. The non-volatile memory cell of claim 1 , wherein the gate of the MOS transistor antifuse element is formed above a conductive layer that shields a channel region that is under a dielectric layer so that the channel region is not altered from a halo implant.
5. The non-volatile memory cell of claim 1 , wherein the non-volatile memory cell is formed in an integrated circuit using standard CMOS processes and wherein the integrated circuit further includes other CMOS circuitry formed using the same standard CMOS processes.
6. The non-volatile memory cell of claim 5 , wherein a dielectric layer that is formed below the gate has an area corresponding to a minimum dimension of the standard CMOS processes used to fabricate the integrated circuit.
7. The non-volatile memory cell of claim 2 , wherein the source and drain of the NMOS transistor antifuse element are surrounded by a dielectric layer.
8. The non-volatile memory cell of claim 7 , wherein the NMOS transistor antifuse element includes p type halo implants adjacent the source and drain and below the gate.
9. The non-volatile memory cell of claim 1 , wherein the source and drain of the MOS transistor antifuse element are surrounded by a dielectric layer.
10. A non-volatile memory cell formed in a semiconductor substrate having a first type of conductivity, comprising:
an antifuse element having a programming node, the antifuse element being configured to have changed resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state; and
a capacitor element coupled to the antifuse element and configured to provide the one or more voltage pulses to the programming node;
wherein the antifuse element is formed in a well having a second type of conductivity that is opposite to the first type of conductivity and includes a source region and a gate region, the source region having the second type of conductivity and being formed in the well and the gate region having the second type of conductivity and being spaced apart from the source region and formed on a dielectric layer that is formed on the well.
11. The non-volatile memory cell of claim 10 , wherein the antifuse element includes halo implants having the first type of conductivity that are formed in the well adjacent the source region.
12. The non-volatile memory cell of claim 11 , wherein the dielectric layer is formed above a conductive layer that shields a channel region that is under the dielectric layer so that the channel region is not altered by the halo implants.
13. The non-volatile memory cell of claim 12 , wherein the gate region and the source region are surrounded by a second dielectric layer.