Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array
View Patent ↗A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage.
1. A method of reading a select non-volatile memory cell from an array of such non-volatile memory cells arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side, wherein alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier, said method comprising:
precharging said global bit lines and local bit lines to a precharged voltage;
connecting one of said first or second global bit lines to a lower voltage, wherein said one global bit line connected to the lower voltage also connects to the local bit line for sensing the select non-volatile memory cell; and
detecting the state of the select non-volatile memory cell by detecting the sense amplifier connected to the global bit line, other than the one global bit line.
2. The method of claim 1 wherein each of the non-volatile memory cells is a bi-directional floating gate non-volatile memory cell.
3. The method of claim 1 wherein each of the non-volatile memory cells is a bi-directional trapping charge layer non-volatile memory cell.
4. The method of claim 2 wherein said non-volatile memory cell is a MLC non-volatile memory cell.
5. The method of claim 3 wherein said non-volatile memory cell is a MLC non-volatile memory cell.
6. The method of claim 1 wherein each of the local bit lines is connectable to one of said global bit lines through a switch.
7. The method of claim 4 further comprising:
activating the switch to connect the local bit line to its associated global bit line for all the local bit lines during the precharging step; and
deactivating the switch to disconnect all local bit lines to their associated global bit lines except for the local bit line for sensing the select non-volatile memory cell, after the precharging step.
8. The method of claim 1 wherein each of said non-volatile memory cells in the same row share a common word line.
9. The method of claim 8 further comprising:
activating the word line connected to the select non-volatile memory cell prior to the detecting step.
10. The method of claim 1 wherein the lower voltage is ground.
11. A non-volatile memory device comprising:
a plurality of bi-directional non-volatile memory cells, each cell having three terminals: a first terminal, a second terminal, and a third terminal;
said plurality of memory cells arranged in a plurality of rows and columns with the first terminal of each cell in the same column connected to and sharing a first local bit line to one side, and with the third terminal of each cell in the same column connected to and sharing a second local bit line to another side, and with the second terminal of each cell in the same row connected to and sharing a common word line;
a plurality of global bit lines;
alternating local bit lines in a row direction are connected to a first global bit line and other alternating local bit lines in the row direction are connected to a second global bit line;
a sense amplifier connected to the first and second global bit lines;
precharging means for precharging said global bit lines and local bit lines to a precharged voltage; and
means for connecting one of said first or second global bit lines to ground, wherein said one global bit line connected to ground also connects to the local bit line for sensing a select non-volatile memory cell.
12. The device of claim 11 further comprising:
each local bit line is connected to the first global bit line or the second global bit line as the case may be through a switch.
13. The device of claim 12 wherein each of the non-volatile memory cells is a bi-directional floating gate non-volatile memory cell.
14. The device of claim 12 wherein each of the non-volatile memory cells is a bi-directional trapping charge layer non-volatile memory cell.
15. The device of claim 13 wherein said non-volatile memory cell is a MLC non-volatile memory cell.
16. The device of claim 14 wherein said non-volatile memory cell is a MLC non-volatile memory cell.
17. A method of programming a select non-volatile memory cell from an array of such non-volatile memory cells arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side, wherein said select non-volatile memory cell is programmed by applying a voltage differential between a first local bit line and a second local bit line, and wherein alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line, said method comprising:
(a) precharging said first and second global bit lines and their associated local bit lines to a first voltage;
(b) connecting one of said first or second global bit line and its associated local bit lines to a second voltage, wherein said associated local bit lines of said one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell, wherein the voltage differential between said second voltage and said first voltage is insufficient to cause programming of said select non-volatile memory cell; and
(c) connecting the bit line, other than the select bit line of the select non-volatile memory cell to a third voltage, wherein the voltage differential between said second voltage and the third voltage is sufficient to cause programming of said select non-volatile memory cell.
18. The method of claim 17 further comprising:
disconnecting the one of said first or second global bit line and its associated local bit lines to the second voltage, immediately prior to connecting step (c).
19. The method of claim 17 wherein the connecting step (b) connects one of the global bit line to the second voltage and wherein the method further comprising:
disconnecting the one global bit line from the select local bit line prior to the connecting step (c).
20. A method of programming a select non-volatile memory cell from an array of such non-volatile memory cells arranged in a plurality of rows and columns, wherein each cell having a first terminal, a second terminal and a third terminal, with the first terminal of each cell in the same column connected to and sharing a first local bit line to one side, and with the third terminal of each cell in the same column connected to and sharing a second local bit line to another side, and with the second terminal of each cell in the same row connected to and sharing a common word line, wherein said select non-volatile memory cell is programmed by applying a voltage differential between its first terminal and its third terminal, and wherein alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line, said method comprising:
(a) charging one of said global bit lines and its associated local bit lines to a first voltage, said associated local bit lines of said one global bit line include a select bit line connected to the first terminal for said select non-volatile memory cell to program said cell;
(b) charging the other of said global bit lines and its associated local bit lines to a second voltage, wherein said second voltage of the local bit lines associated with said other global bit line being capacitively coupled to said select bit line boosting said first voltage to a third voltage;
(c) disconnecting said other global bit line and its associated local bit lines from said third terminal of the select non-volatile memory cell; and
(d) connecting said third terminal of the select non-volatile memory cell to a fourth voltage, wherein the voltage differential between the third voltage and the fourth voltage is sufficient to cause programming of said select non-volatile memory cell.
21. The method of claim 20 wherein said charging step (a) precedes the charging step (b).
22. The method of claim 20 wherein said charging step (b) precedes the charging step (a).