Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric
View Patent ↗A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
1. A method of making an electrically programmable and erasable memory device, comprising:
forming an electrically conductive floating gate disposed over and insulated from a memory area of a substrate;
forming an insulating layer that has a first portion formed over the memory area of the substrate and a second portion formed over a peripheral area of the substrate, wherein the insulating layer first portion has a thickness permitting Fowler-Nordheim tunneling of charges therethrough;
changing a thickness of one of the insulating layer first and second portions such that the insulating layer first and second portions have unequal thicknesses;
forming an electrically conductive control gate disposed adjacent to the floating gate and insulated therefrom by the first portion of the insulating layer; and
forming an electrically conductive poly gate disposed over the peripheral area of the substrate and insulated therefrom by the second portion of the insulating layer.
2. The method of claim 1 , further comprising:
forming a first source region and a first drain region in the substrate, with a first channel region therebetween, wherein the floating gate is disposed over and insulated from at least a portion of the first channel region; and
forming a second source region and a second drain region in the substrate, with a second channel region therebetween, wherein the poly gate is disposed over and insulated from at least a portion of the second channel region.
3. The method of claim 1 , wherein the formation of the control gate and the poly gate includes:
depositing a layer of conductive material over the insulating layer; and
selectively removing portions of deposited conductive material except for a first portion thereof forming the control gate and a second portion thereof forming the poly gate.
4. The method of claim 1 , wherein the changing of the thickness of one of the insulating layer first and second portions includes:
forming a layer of material over the insulating layer;
masking a first portion of the layer of material formed over the first portion of the insulating layer, wherein a second portion of the layer of material formed over the second portion of the insulating layer is left unmasked;
removing the unmasked second portion of the layer of material to expose the second portion of the insulating layer; and
increasing the thickness of the exposed second portion of the insulating layer.
5. The method of claim 4 wherein the increasing of the thickness of the exposed insulating layer second portion includes thermally oxidizing the exposed insulating layer second portion.
6. The method of claim 1 , wherein the changing of the thickness of one of the insulating layer first and second portions includes:
forming a layer of material over the insulating layer;
masking a first portion of the layer of material formed over the second portion of the insulating layer, wherein a second portion of the layer of material formed over the first portion of the insulating layer is left unmasked;
removing the unmasked second portion of the layer of material to expose the first portion of the insulating layer; and
removing a top portion of the exposed first portion of the insulating layer.
7. A method of forming an electrically programmable and erasable memory device, comprising:
forming a memory cell in a memory area of a substrate, wherein the memory cell formation includes:
forming a floating gate over and insulated from the substrate, and
forming a control gate adjacent to and insulated from the floating gate;
forming an MOS transistor in a peripheral area of the substrate, wherein the MOS transistor formation includes forming a poly gate over and insulated from the substrate;
wherein the formation of the memory cell and the formation of the MOS transistor together include:
forming an insulating layer having a first portion that is disposed between the control gate and the floating gate with a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and a second portion that is disposed between the poly gate and the substrate, wherein the second portion of the insulating layer has a thickness that is greater than that of the first portion of the insulating layer.
8. The method of claim 7 , further comprising:
forming first source and drain regions with a first channel region therebetween in the substrate, wherein the floating gate is disposed over at least a portion of the first channel region; and
forming second source and drain regions with a second channel region therebetween in the substrate, wherein the poly gate is disposed over at least a portion of the second channel region.
9. The method of claim 7 , wherein the formation of the insulating layer includes:
forming the first and second portions of the insulating layer with a uniform thickness over the memory and peripheral areas of the substrate; and
changing the thickness of one of the insulating layer first and second portions such that the insulating layer first and second portions have unequal thicknesses.
10. The method of claim 9 , wherein the changing of the thickness of one of the insulating layer first and second portions includes:
forming a layer of material over the insulating layer;
masking a first portion of the layer of material formed over the insulating layer first portion, wherein a second portion of the layer of material formed over the second portion of the insulating layer is left unmasked;
removing the unmasked second portion of the layer of material to expose the insulating layer second portion; and
increasing the thickness of the exposed second portion of the insulating layer.
11. The method of claim 10 wherein the increasing of the thickness of the exposed insulating layer second portion includes thermally oxidizing the exposed insulating layer second portion.
12. The method of claim 9 , wherein the changing of the thickness of one of the insulating layer first and second portions includes:
forming a layer of material over the insulating layer;
masking a first portion of the layer of material formed over the second portion of the insulating layer, wherein a second portion of the layer of material formed over the first portion of the insulating layer is left unmasked;
removing the unmasked second portion of the layer of material to expose the first portion of the insulating layer; and
removing a top portion of the exposed first portion of the insulating layer.
13. A method of forming an electrically programmable and erasable memory device, comprising:
forming a memory cell in a memory area of a substrate, wherein the memory cell formation includes:
forming a floating gate over and insulated from the substrate, and
forming a control gate adjacent to and insulated from the floating gate;
forming an MOS transistor in a peripheral area of the substrate, wherein the MOS transistor formation includes forming a poly gate over and insulated from the substrate;
wherein the formation of the memory cell and the formation of the MOS transistor together include:
forming an insulating layer having a first portion that is disposed between the control gate and the floating gate with a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and a second portion that is disposed between the poly gate and the substrate, wherein the second portion of the insulating layer has a thickness that is greater than that of the first portion of the insulating layer; and
wherein the formation of the control gate and the poly gate includes:
depositing a layer of conductive material over the insulating layer; and
selectively removing portions of deposited conductive material except for a first portion thereof forming the control gate and a second portion thereof forming the poly gate.