Array of floating gate memory cells having strap regions and a peripheral logic device region
View Patent ↗A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that are filled with a conducting material such as metal or metalized polysilicon to form blocks of the conducting material that constitute source lines. Each source line extends over and is electrically connected to one of the source regions in each of the active regions.
1. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of memory cells, each of the memory cells including:
first and second spaced apart regions in the substrate having a second conductivity type, with a channel region defined in the substrate therebetween,
an electrically conductive floating gate disposed over and insulated from a portion of the channel region, and
an electrically conductive control gate disposed over and insulated from a portion of the channel region;
a plurality of source line blocks of metal material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks extends over and is electrically connected to one of the first regions in each of the active regions;
a first plurality of parallel spaced apart lines of conductive material formed over the substrate and electrically connected to the control gates of the memory cells;
a plurality of strap regions each formed on the substrate and disposed in an interlaced fashion between selected ones of the active regions, each of the strap regions including:
first strap cells through which the first plurality of conductive material lines traverse, wherein the first plurality of conductive material lines completely traverse across the strap region,
a first plurality of conductive metal contacts each of which is connected to one of the first plurality of conductive material lines in one of the first strap cells,
second strap cells in which the source line blocks terminate without completely traversing across the strap region, and
a second plurality of conductive metal contacts each of which is connected to one of the source line blocks in one of the second strap cells.
2. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of memory cells, each of the memory cells including:
first and second spaced apart regions in the substrate having a second conductivity type, with a channel regions defined in the substrate therebetween,
an electrically conductive floating gate disposed over and insulated from a portion of the channel region, and
an electrically conductive control gate disposed over and insulated from a portion of the channel region;
a plurality of source line blocks of metal material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks extends over and is electrically connected to one of the first regions in each of the active regions;
wherein for each of the memory cells, the control gate includes:
a first portion disposed laterally adjacent to and insulated from the floating gate,
a second portion extending over and insulated from a portion of the floating gate, and
a substantially planar sidewall portion.
3. The array of claim 2 , wherein each of the memory cells includes a conductive layer of TiN disposed between the first region and the source line block electrically connected thereto.
4. The array of claim 2 , wherein each of the memory cells further comprises:
a conductive contact electrically connected to the second region, wherein the conductive contact includes a first portion disposed laterally adjacent to and insulated from the planar sidewall portion of the control gate, and a second portion disposed over and insulated from at least a portion of the control gate.
5. The array of claim 2 , wherein each of the memory cells further comprises:
a layer of metalized silicon formed on the second region; and
a layer of metalized polysilicon formed on a top surface of the control gate.
6. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and
each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs including:
a first region and a pair of second regions spaced apart in the substrate having a second conductivity type, with channel regions defined in the substrate between the first region and the second regions,
a pair of electrically conductive floating gates each disposed over and insulated from a portion of one of the channel regions, and
a pair of electrically conductive control gates each disposed over and insulated from a portion of one of the channel regions; and
a plurality of source line blocks of metal material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks extends over and is electrically connected to one of the first regions in each of the active regions.
7. The array of claim 6 , wherein each of the memory cell pairs includes a conductive layer of TiN disposed between the first region and the source line block electrically connected thereto.
8. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs including:
a first region and a pair of second regions spaced apart in the substrate having a second conductivity type, with channel regions defined in the substrate between the first region and the second regions,
a pair of electrically conductive floating gates each disposed over and insulated from a portion of one of the channel regions, and
a pair of electrically conductive control gates each disposed over and insulated from a portion of one of the channel regions;
a plurality of source line blocks of metal material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks extends over and is electrically connected to one of the first regions in each of the active regions;
a first plurality of parallel spaced apart lines of conductive material formed over the substrate and electrically connected to the control gates of the memory cells;
a plurality of strap regions each formed on the substrate and disposed in an interlaced fashion between selected ones of the active regions, each of the strap regions including:
first strap cells through which the first plurality of conductive material lines traverse, wherein the first plurality of conductive material lines completely traverse across the strap region,
a first plurality of conductive metal contacts each of which is connected to one of the first plurality of conductive material lines in one of the first strap cells,
second strap cells in which the source line blocks terminate without completely traversing across the strap region, and
a second plurality of conductive metal contacts each of which is connected to one of the source line blocks in one of the second strap cells.
9. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs including:
a first region and a pair of second regions spaced apart in the substrate having a second conductivity type, with channel regions defined in the substrate between the first region and the second regions,
a pair of electrically conductive floating gates each disposed over and insulated from a portion of one of the channel regions, and
a pair of electrically conductive control gates each disposed over and insulated from a portion of one of the channel regions;
a plurality of source line blocks of metal material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks extends over and is electrically connected to one of the first regions in each of the active regions;
wherein for each of the memory cell pairs, the control gates each include:
a first portion disposed laterally adjacent to and insulated from one of the floating gates,
a second portion extending over and insulated from a portion of the one floating gate, and
a substantially planar sidewall portion.
10. The array of claim 9 , wherein each of the memory cell pairs further comprises:
a pair of conductive contacts each electrically connected to one of the second regions, wherein each of the conductive contacts includes a first portion disposed laterally adjacent to and insulated from the planar sidewall portion of one of the control gates, and a second portion disposed over and insulated from at least a portion of the one control gate.
11. The array of claim 9 , wherein each of the memory cell pairs further comprises:
a layer of metalized silicon formed on each of the second regions; and
a layer of metalized polysilicon formed on a top surface of each of the control gates.
12. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs including:
a first region and a pair of second regions spaced apart in the substrate having a second conductivity type, with channel regions defined in the substrate between the first region and the second regions,
a pair of electrically conductive floating gates each disposed over and insulated from a portion of one of the channel regions, and
a pair of electrically conductive control gates each disposed over and insulated from a portion of one of the channel regions; and
a plurality of source line blocks of material each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction, wherein each of the source line blocks:
extends over and is electrically connected to one of the first regions in each of the active regions, and
comprises a polysilicon layer of material and a metalized polysilicon layer of material.
13. The array of claim 12 , wherein for each of the memory cell pairs, the source line block connected thereto extends from the first region to a height above the substrate that exceeds a height above the substrate of the control gates.