Method and apparatus for testing the connectivity of a flash memory chip
View Patent ↗In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
1. An integrated circuit, comprising:
a substrate;
a flash memory array fabricated on the substrate;
a plurality of bond pads fabricated on the substrate;
a plurality of boundary scan cells fabricated on the substrate each in electronic communication with an associated one of the bond pads, wherein each boundary scan cell of the plurality of boundary scan cells is configured to transmit test data to the associated bond pad so as to test an electrical connection between the associated bond pad and the flash memory array; and
a scanning element associated with at least one of the plurality of boundary scan cells, wherein the scanning element and a comparator are configured to verify the contents of the memory cells;
wherein the integrated circuit is configured to store test data within the memory array, retrieve the test data as result data at the pins, and indicate a connectivity error within the flash memory array if result data from a path through the flash memory array does not correspond to the test data.
2. The integrated circuit of claim 1 wherein the plurality of boundary scan cells are further configured to receive from the flash memory array result data corresponding to the transmitted test data, the result data resulting from testing for errors within the memory array.
3. The integrated circuit of claim 2 wherein the result data comprises binary information, and wherein the boundary scan cells of the plurality of boundary scan cells are further configured with a comparator to identify the binary information.
4. The integrated circuit of claim 2 wherein the boundary scan cells of the plurality of boundary scan cells are serially interconnected, and are further configured to serially shift the received test data and the result data to an adjacent one of the boundary scan cells.
5. The integrated circuit of claim 1 wherein the plurality of boundary scan cells is configured according to IEEE Standard 1149.1-2006.
6. The integrated circuit of claim 1 wherein the flash memory array further comprises a plurality of source side injection flash memory cells.
7. The integrated circuit of claim 1 wherein the flash memory array further comprises a plurality of multilevel memory cells.
8. The integrated circuit of claim 1 further comprising a first register configured to store the test data and to store result data corresponding to the transmitted test data, and a second register in communication with the first register, the second register configured to receive the test data from the first register, and to latch the test data for transmission to the flash memory array.
9. The integrated circuit of claim 8 wherein the first registers of the plurality of boundary scan cells are serially interconnected, and wherein each of the first registers is further configured to shift the result data to the first register of a serially interconnected one of the boundary scan cells.
10. The integrated circuit of claim 8 further comprising a comparator in communication with the first register, the comparator configured to determine whether the first register data corresponds to the second register data.
11. An integrated circuit, comprising:
a substrate;
a flash memory array fabricated on the substrate;
a plurality of bond pads fabricated on the substrate; and
a plurality of boundary scan cells fabricated on the substrate each in electronic communication with an associated one of the bond pads, wherein each boundary scan cell of the plurality of boundary scan cells is configured to transmit test data to the associated bond pad so as to test an electrical connection between the associated bond pad and the flash memory array;
wherein the integrated circuit is configured to:
store the test data in the flash memory array;
retrieve, from the flash memory array to one or more boundary scan cells, a retrieved set of the test data from a path through the memory array, wherein the retrieved set of the test data is the test data resulting from storage within and extraction from the flash memory array; and
comparing the retrieved set of the test data with the test data so as to determine if the flash memory array used to store the test data is free of errors.
12. The integrated circuit of claim 11 wherein the plurality of boundary scan cells are further configured to receive from the flash memory array result data corresponding to the transmitted test data, the result data resulting from testing for errors within the memory array.
13. The integrated circuit of claim 12 wherein the result data comprises binary information, and wherein the boundary scan cells of the plurality of boundary scan cells are further configured with a comparator to identify the binary information.
14. The integrated circuit of claim 12 wherein the boundary scan cells of the plurality of boundary scan cells are serially interconnected, and are further configured to serially shift the received test data and the result data to an adjacent one of the boundary scan cells.
15. The integrated circuit of claim 11 further comprising a first register configured to store the test data and to store result data corresponding to the transmitted test data, and a second register in communication with the first register, the second register configured to receive the test data from the first register, and to latch the test data for transmission to the flash memory array.
16. The integrated circuit of claim 15 wherein the first registers of the plurality of boundary scan cells are serially interconnected, and wherein each of the first registers is further configured to shift the result data to the first register of a serially interconnected one of the boundary scan cells.
17. The integrated circuit of claim 15 further comprising a comparator in communication with the first register, the comparator configured to determine whether the first register data corresponds to the second register data.
18. The integrated circuit of claim 11 wherein the plurality of boundary scan cells is configured according to IEEE Standard 1149.1-2006.
19. The integrated circuit of claim 11 wherein the flash memory array further comprises a plurality of source side injection flash memory cells.
20. The integrated circuit of claim 11 wherein the flash memory array further comprises a plurality of multilevel memory cells.