Ring oscillator for digital multilevel non-volatile memory
View Patent ↗An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.
1. A ring oscillator comprising:
a plurality of first inverters coupled in series with an output of one first inverter coupled to the input of another first inverter to form a ring, each of said plurality of inverters providing a first inverted signal having characteristics dependent on an applied first bias current, one of said first inverters providing a first clock signal;
a plurality of first capacitors, each of said plurality of first capacitors being coupled to the output of a respective one of said plurality of first inverters;
a second inverter having an input coupled to the output of said one of said plurality of first inverter providing said first clock signal and having an output for providing a second clock signal having characteristics dependent on an applied second bias current, the ratio of first bias current to the second bias current being such to adjust the phase between the first and second clock signals to a pre-selected value; and
a second capacitor coupled to the output of the second inverter, the capacitance of each of the plurality of first capacitors being equal to the capacitance of the second capacitor.
2. The ring oscillator of claim 1 further comprising a phase driver circuit for generating first and second driver signals in response to the first and second clock signals, the first and second driver signals being nonoverlapping clock signals.
3. The ring oscillator of claim 1 further comprising a phase driver circuit for generating first and second driver signals in response to the first and second clock signals, the first and second driver signals being phased apart clock signals.
4. A ring oscillator, comprising:
a plurality of first inverters coupled in series with an output of one first inverter coupled to the input of another first inverter to form a ring, one of said first inverters providing a first clock signal;
a plurality of first capacitors, each of said plurality of first capacitors being coupled to the output of a respective one of said plurality of first inverters;
a second inverter having an input coupled to the output of said one first inverter providing said first clock signal and having an output for providing a second clock signal;
a second capacitor counted to the output of the second inverter, the ratio of a capacitance of the second capacitor to a capacitance of the first capacitors being such to adjust the phase between the first and second clock signals to a pre-selected value; and
a phase driver circuit for generating first and second driver signals in response to the first and second clock signals, the first and second driver signals being nonoverlapping clock signals.
5. A ring oscillator, comprising:
a plurality of first inverters coupled in series with an output of one first inverter coupled to the input of another first inverter to font a ring, one of said first inverters providing a first clock signal;
a plurality of first capacitors, each of said plurality of first capacitors being coupled to the output of a respective one of said plurality of first inverters;
a second inverter having an input coupled to the output of said one first inverter providing said first clock signal and having an output for providing a second clock signal;
a second capacitor coupled to the output of the second inverter, the ratio of a capacitance of the second capacitor to a capacitance of the first capacitors being such to adjust the phase between the first and second clock signals to a pre-selected value; and
a phase driver circuit for generating first and second driver signals in response to the first and second clock signals, the first and second driver signals being phased apart clock signals.