Semiconductor memory array of floating gate memory cells with control gate spacer portions
View Patent ↗A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions by forming a conductive layer of material. Trenches are formed in the row direction across the active regions, and are filled with a conductive material to form blocks of conductive material that are the control gates. Sidewall spacers of conductive material are formed along the floating gate blocks to give the floating gates protruding portions that extend over the floating gate.
1. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material of a first conductivity type,
first and second spaced-apart terminals in the substrate of a second conductivity tupe, with a channel region therebetween;
a first insulation layer disposed over said substrate;
an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal;
a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and
an electrically conductive control gate having a first portion and a second portion, the first portion being substantially rectangularly shaped and positioned immediately adjacent to the second insulation layer, the second portion being substantially a spacer connected to the first portion and disposed over the floating gate and insulated therefrom.
2. The device of claim 1 , wherein the control gate forms a notch at the connection between the first portion and the second portion.
3. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a column of memory cells extending in the first direction, each of the memory cells including:
first and second spaced-apart terminals formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween,
a first insulation layer disposed over said substrate including over said channel region,
an electrically conductive floating gate disposed over said first insulation layer and extending over portion of said channel region and over a portion of the second terminal, and
a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and
a plurality of electrically conductive control gates each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction and having a first portion that is substantially rectangular in shape and a second portion that is connected to the first portion and is substantially a spacer, wherein each of the control gates intercepts one of the memory cells in each of the active regions such that the first portion is positioned immediately adjacent to the second insulation layer and therein and the second portion is disposed over the floating gate and insulated therefrom.
4. The device of claim 3 , wherein the control gate forms a notch at the connection between the first portion and the second portion.
5. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material of a first conductivity type;
first and second spaced-apart terminals in the substrate of a second conductivity type, with a channel region therebetween;
a first insulation layer disposed over said substrate;
an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal;
a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and
an electrically conductive control gate having a first portion and a second portion, the first portion having a substantially planar sidewall portion and is positioned immediately adjacent to the second insulation layer, the second portion being substantially a spacer connected to the substantially planar sidewall portion and disposed over the floating gate and insulated therefrom.
6. The device of claim 5 , wherein the control gate forms a notch at the connection between the first portion and the second portion.
7. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a column of memory cells extending in the first direction, each of the memory cells including:
first and second spaced-apart terminals formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween,
a first insulation layer disposed over said substrate including over said channel region,
an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal, and
a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling charges therethrough; and
a plurality of electrically conductive control gates each extending across the active regions and isolation regions in a second direction substantially perpendicular to the first direction and having a first portion that has a substantially planar sidewall portion and a second portion that is connected to the substantially planar sidewall portion and is substantially a spacer, wherein each of the control gates intercepts one of the memory cells in each of the active regions such that the first portion is positioned immediately adjacent to the second insulation layer therein and the second portion is disposed over the floating gate and insulated therefrom.
8. The device of claim 7 , wherein the control gate forms a notch at the connection between the first portion and the second portion.