Transistor design for use in advanced nanometer flash memory devices
Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.
1. A decoder for use in a memory device, comprising:
a plurality of receiving blocks, each receiving block configured to receive one bit of data from a bit line, wherein each receiving block comprises an N-LDE1 transistor coupled to the bit line and an N-LDE2 transistor coupled to the bit line and to ground; and
an output block coupled to an N-LDE1 transistor in each of the plurality of receiving blocks for generating an output;
wherein each N-LDE1 transistor is an NMOS transistor comprising a source with a first shallow trench isolation area width of 0.2-0.3 μm, a drain with a second shallow trench isolation area width of 0.2-0.3 μm, a first gate, a distance between a first edge of the first gate and the closest edge of the first shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the first gate and the closest edge of the second shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and
wherein each N-LDE2 transistor is an NMOS transistor comprising a source with a third shallow trench isolation area width of 0.2-0.3 μm, a drain with a fourth shallow trench isolation area width of 0.2-0.3 μm, a second gate, a distance between a first edge of the second gate and the closest edge of the third shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the second gate and the closest edge of the fourth shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source.
2. The decoder of claim 1 , wherein the output block comprises an N-LDE1 transistor and an N-LDE2 transistor.
3. A decoder for use with a flash memory array, comprising:
a plurality of receiving blocks, each receiving block configured to receive one bit of data from a bit line of the flash memory array, wherein each receiving block comprises an N-LDE1 transistor coupled to the bit line and an N-LDE2 transistor coupled to the bit line and to ground; and
an output block coupled to an N-LDE1 transistor in each of the plurality of receiving blocks for generating an output;
wherein each N-LDE1 transistor is an NMOS transistor comprising a source with a first shallow trench isolation area width of 0.2-0.3 μm, a drain with a second shallow trench isolation area width of 0.2-0.3 μm, a first gate, a distance between a first edge of the first gate and the closest edge of the first shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the first gate and the closest edge of the second shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and
wherein each N-LDE2 transistor is an NMOS transistor comprising a source with a third shallow trench isolation area width of 0.2-0.3 μm, a drain with a fourth shallow trench isolation area width of 0.2-0.3 μm, a second gate, a distance between a first edge of the second gate and the closest edge of the third shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the second gate and the closest edge of the fourth shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source.
4. The decoder of claim 3 , wherein the output block comprises an N-LDE1 transistor and an N-LDE2 transistor.
5. A decoder for use in a memory device, comprising:
at least eight receiving blocks, each receiving block configured to receive one bit of data from a bit line, wherein each receiving block comprises an N-LDE1 transistor coupled to the bit line and an N-LDE2 transistor coupled to the bit line and to ground; and
an output block coupled to an N-LDE1 transistor in each of the at least eight receiving blocks for generating an output;
wherein each N-LDE1 transistor is an NMOS transistor comprising a source with a first shallow trench isolation area width of 0.2-0.3 μm, a drain with a second shallow trench isolation area width of 0.2-0.3 μm, a first gate, a distance between a first edge of the first gate and the closest edge of the first shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the first gate and the closest edge of the second shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and
wherein each N-LDE2 transistor is an NMOS transistor comprising a source with a third shallow trench isolation area width of 0.2-0.3 μm, a drain with a fourth shallow trench isolation area width of 0.2-0.3 μm, a second gate, a distance between a first edge of the second gate and the closest edge of the third shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the second gate and the closest edge of the fourth shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source.
6. The decoder of claim 5 , wherein the output block comprises an N-LDE1 transistor and an N-LDE2 transistor.