IP Library Granted Patent US 7,434,092
Granted Patent B2
US 7,434,092 · App. 11/063,316 · Granted Oct 7, 2008

Semiconductor memory and method of storing configuration data

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Quick Facts
Patent No.
US 7,434,092
App. No.
11/063,316
Granted
Oct 7, 2008
Kind
B2
Abstract

Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.

Claims (15)

1. A semiconductor memory with redundancy repair, comprising a main memory array, configuration data stored in an area of the array which is known to be unrepaired, and a signature code that verifies the validity of the configuration data and is stored in the unrepaired area as a pointer to the configuration data.

2. The semiconductor memory of claim 1 wherein the signature code is stored at a known address.

3. The semiconductor memory of claim 1 wherein the area in which the configuration data is stored is part of a configuration page having a plurality of areas which are known to be unrepaired and which can be utilized to store repair information during testing of the memory, the number of areas in the configuration page being greater than the number of repairs permitted to be made in the memory array.

4. A semiconductor memory with redundancy repair, comprising a main memory array, a configuration page divided into a plurality of storage areas, data for configuration of the memory stored in one of the storage areas which has been tested and found to be free of bad bits, and a signature code stored with the configuration data in the area which is free of bad bits.

5. The semiconductor memory of claim 4 wherein the number of storage areas in the configuration page is greater than the number of repairs permitted to be made in the memory array.

6. The semiconductor memory of claim 4 wherein each of the storage areas starts at a known address of the memory array.

7. A method of storing configuration data for a semiconductor memory in which defective areas of a main memory array are repaired redundantly, comprising the steps of: identifying an area of the main memory array which has not been repaired, storing configuration data for the memory in the unrepaired area, and storing a signature code that verifies the validity of the configuration data in the unrepaired area as a pointer to the configuration data.

8. The method of claim 7 wherein the signature code is stored at a known address in the memory array.

9. A method of storing configuration data for a semiconductor memory in which defective areas of a main memory array are repaired redundantly, comprising the steps of: setting up a configuration page in the main memory array, with the configuration page being divided into a plurality of areas of equal size and known starting addresses, testing the areas in the configuration page to identify an area which is free of bad bits, storing configuration data in the area which is free of bad bits, and storing a signature code in the area of the configuration rage with the configuration data.

10. The method of claim 9 including the step of erasing the configuration page before storing the configuration data.

11. A method of configuring a semiconductor memory in which defective areas of a main memory array are repaired redundantly, the steps of: setting up a configuration page in the main memory array, with the configuration page being divided into a plurality of areas with known starting addresses, storing configuration data in one of the areas of the configuration page which is known to be free of bad bits, storing a signature code in the area of the configuration page with the configuration data, addressing the areas of the configuration page until the signature code is found, and reading the configuration data from the area where the signature code is found.

12. The method of claim 11 wherein the areas of the configuration page are of equal size.

13. The method of claim 11 including the step of storing repair information as repairs are made.

14. A configuration memory for a semiconductor memory having a main memory array which can be redundantly repaired, comprising: a configuration page divided into a plurality of storage areas of equal size and known starting addresses, configuration data stored in one of the areas which is known to be free of bad bits, and a signature code stored in the area with the configuration data for verifying the validity of the configuration data.

15. The configuration memory of claim 14 wherein the configuration page is an integral part of the main memory array.

Assignments (16)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 059687/0344 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: SILICON STORAGE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0316 →
NUNC PRO TUNC ASSIGNMENT Recorded Jun 14, 2006
From: ACTRANS SYSTEM INCORPORATION, USA
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 017776/0759 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2005
From: WANG, CHIH-CHIEH; PABUSTAN, JONATHAN G.; SHEEN, BEN
To: ACTRANS SYSTEM INCORPORATION, USA
Reel/Frame 016315/0782 →