Method and system for gallium nitride electronic devices using engineered substrates
View Patent ↗A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.
1. A vertical III-nitride electronic device comprising:
a first electrical contact structure;
a III-nitride epitaxial buffer layer of a first conductivity type contacting the first electrical contact structure;
a III-nitride epitaxial drift layer contacting the III-nitride epitaxial buffer layer; and
a second electrical contact structure contacting the III-nitride epitaxial drift layer.
2. The vertical III-nitride electronic device of claim 1 wherein the III-nitride epitaxial buffer layer comprises an n-type GaN layer.
3. The vertical III-nitride electronic device of claim 1 wherein the first conductivity type comprises an n-type.
4. The vertical III-nitride electronic device of claim 1 wherein the III-nitride epitaxial drift layer comprises an n-type GaN layer and one or more additional GaN layers.
5. The vertical III-nitride electronic device of claim 1 wherein a thickness of the III-nitride epitaxial buffer layer and the III-nitride epitaxial buffer layer is between about 1 μm and about 100 μm.
6. The vertical III-nitride electronic device of claim 1 further comprising a device substrate supporting the first electrical contact structure.
7. A vertical III-nitride JFET comprising:
a device substrate;
an interface layer coupled to the device substrate;
a first electrode structure coupled to the interface layer;
a III-nitride epitaxial layer connected to the first electrode structure;
a III-nitride drift layer epitaxially coupled to the III-nitride epitaxial layer;
a III-nitride channel region epitaxially coupled to the III-nitride drift layer;
a III-nitride source region epitaxially coupled to the III-nitride channel region; and
one or more gate regions disposed adjacent the III-nitride channel region,
wherein the interface layer, the first electrode structure, the III-nitride epitaxial layer, the III-nitride drift layer, the III-nitride channel region, and the III-nitride source region are all on the same side of the substrate.
8. The vertical III-nitride JFET of claim 7 further comprising a source electrode structure coupled to the III-nitride source region.
9. The vertical III-nitride JFET of claim 7 further comprising one or more gate electrode structures coupled to the one or more gate regions.
10. The vertical III-nitride JFET of claim 7 wherein a thickness of the interface layer ranges from about 0.1 μm to about 1 μm.
11. The vertical III-nitride JFET of claim 7 wherein a thickness of the III-nitride drift layer ranges from about 1 μm to about 100 μm.
12. The vertical III-nitride JFET of claim 7 wherein a distance measured from the first electrode structure to the III-nitride drift layer is less than 10 μm.
13. The vertical III-nitride JFET of claim 7 wherein the III-nitride epitaxial layer and the III-nitride drift layer are silicon-doped n-type layers.
14. The vertical III-nitride JFET of claim 7 wherein the III-nitride epitaxial layer and the III-nitride drift layer are characterized by an oxygen concentration less than 2×10 18 cm −3 .
15. The vertical III-nitride JFET of claim 13 wherein the III-nitride epitaxial layer is characterized by a silicon concentration greater than 1×10 18 cm −3 .