Circuit and method for refreshing a memory module
View Patent ↗A circuit is configured to be operatively coupled to a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The circuit is configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The circuit can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.
1. A circuit comprising:
a first set of signal lines configured to be operatively coupled to a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks;
a second set of signal lines configured to be operatively coupled to a memory controller of a computer system to receive, for a logical rank of the one or more logical ranks, a logical rank refresh command generated by the memory controller,
wherein the circuit is configured to initiate, in response to the logical rank refresh command, a first refresh operation for one or more first physical ranks of the set of at least two physical ranks and a second refresh operation for one or more second physical ranks of the set of at least two physical ranks, wherein the second refresh operation is initiated after the first refresh operation; and
wherein the circuit is further configured to cause a refresh time (tRFC) value to be stored in a memory location accessible by the memory controller, the tRFC value being based at least in part on a calculated maximum amount of time for refreshing the logical rank.
2. The circuit of claim 1 , wherein the memory location resides in a serial presence detect (SPD) device accessible by the memory controller, and wherein the circuit is configured to cause the tRFC value to be stored in the SPD device.
3. The circuit of claim 1 , wherein the circuit is configured to calculate the tRFC value.
4. The circuit of claim 3 , wherein the circuit is configured to calculate the tRFC value in response to at least a maximum amount of time it takes to refresh a physical rank, the number of physical ranks per logical rank, and a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus.
5. The circuit of claim 4 , wherein the circuit is configured to calculate the tRFC value according to the equation:
tRFC =( PR _refresh_time*num — PR _per — LR )+(bus_wait*clk_per)
where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, bus_wait is a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus, and clk_per is a system clock period.
6. The circuit of claim 5 , wherein ratio of the number of physical ranks to the number of logical ranks is two.
7. The circuit of claim 3 , wherein the circuit is configured to calculate the tRFC value at least in part based on a four activate window (tFAW) value.
8. The circuit of claim 7 , wherein the circuit is configured to calculate the tRFC value according to the equation:
tRFC ≧( PR _refresh_time*num — PR _per — LR )+( tFAW −num_open_slots)*clk_per
where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, tFAW is the four activate window value, and num_open_slots is a minimum number of open slots within the tFAW in which there is not a memory controller command on the command bus, and clk_per is a system clock period.
9. The circuit of claim 1 , wherein the one or more first physical ranks comprise at least two physical ranks and the one or more second physical ranks comprise of at least two physical ranks.
10. The circuit of claim 9 , wherein ratio of the number of physical ranks to the number of logical ranks is 4, 8, or 16.
11. The circuit of claim 1 , wherein the one or more first physical ranks comprise N physical ranks configured to be refreshed concurrently with one another and wherein the one or more second physical ranks comprise N physical ranks configured to be refreshed concurrently with one another, where N is a number greater than or equal to two.
12. The circuit of claim 11 , wherein the circuit is configured to calculate the tRFC value according to the equation:
tRFC
=
(
PR_refresh
_time
*
num_PR
_per
_LR
N
)
+
(
⌊
num_PR
_per
_LR
-
1
N
⌋
*
refresh_wait
_time
)
,
where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, and refresh_wait_time is an amount of delay inserted after each physical rank refresh.
13. The circuit of claim 1 , wherein the memory devices are DDR memory devices wherein the circuit is configured to be mounted on a printed circuit board having the plurality of memory devices mounted on the printed circuit board, wherein the printed circuit board is configured to be operatively coupled to the memory controller.
14. The circuit of claim 1 , wherein each logical rank comprises an address space which is mapped into an address space of a set of at least two of the plurality of physical ranks.
15. A method of using a circuit, comprising:
providing a circuit operatively coupled to a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks;
receiving a command to refresh a logical rank of the one or more logical ranks;
initiating a refresh operation for one or more first physical ranks of the set of physical ranks corresponding to the logical rank in response to the command; and
initiating a refresh operation for one or more second physical ranks of the set of physical ranks corresponding to the logical rank in response to the command; and
storing a refresh time (tRFC) value in a memory location accessible by the memory controller, the tRFC value based at least in part on a calculated maximum amount of time for refreshing the logical rank.
16. The method of claim 15 , wherein the tRFC value is calculated in response to at least a maximum amount of time it takes to refresh a physical rank, the number of physical ranks per logical rank, and a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus.
17. The method of claim 16 , wherein the tRFC value is calculated according to the equation:
tRFC =( PR _refresh_time*num — PR _per — LR )+(bus_wait*clock_per)
where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, bus_wait is a maximum number of continuous clock cycles that commands generated by the memory controller can occupy the command bus, and clock_per is a system clock period.
18. The method of claim 17 , wherein the tRFC value is calculated at least in part based on a four activate window (tFAW) value.
19. The method of claim 18 , wherein the tRFC value is calculated according to the equation:
tRFC ≧( PR _refresh_time*num — PR _per — LR )+( tFAW −num_open_slots)*clk_per
where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, tFAW is the four activate window value, and num_open_slots is a minimum number of open slots within the tFAW in which there is not a memory controller command on the command bus, and clk_per is a system clock period.
20. The method of claim 16 , further comprising calculating the tRFC value prior to storing the tRFC value in the memory location of the memory module.
21. The method of claim 15 , wherein the one or more first physical ranks comprise N physical ranks configured to be refreshed concurrently with one another and wherein the one or more second physical ranks comprise N physical ranks configured to be refreshed concurrently with one another, where N is a number greater than or equal to two.
22. The method of claim 21 , wherein the tRFC value is calculated according to the equation:
tRFC
=
(
PR_refresh
_time
*
num_PR
_per
_LR
N
)
+
(
⌊
num_PR
_per
_LR
-
1
N
⌋
*
refresh_wait
_time
)
where PR_refresh_time is an amount of time it takes to refresh a physical rank, num_PR_per_LR is the number of physical ranks corresponding to a logical rank, and refresh_wait_time is an amount of delay inserted after each physical rank refresh.
23. A method of operating a memory module, comprising:
accessing a memory location on the memory module storing a refresh time (tRFC) value, the tRFC value based at least in part on a calculated maximum amount of time for refreshing a logical rank of the memory module, the logical rank corresponding to a set of at least two physical ranks;
transmitting a refresh command to the memory module instructing the memory module to refresh the logical rank, the refresh command causing a circuit on the memory module to initiate a first refresh operation for one or more first physical ranks of the set of at least two physical ranks and to initiate a second refresh operation for one or more second physical ranks of the set of at least two physical ranks, wherein the second refresh operation is initiated after the first refresh operation; and
after transmitting the refresh command to the memory module, waiting for an amount of time corresponding to at least the tRFC value before issuing a subsequent command to the memory module.
24. The method of claim 23 , wherein the receiving, transmitting and waiting are performed by a memory controller of a computer system.