Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition
Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.
1. A transistor device, comprising:
an insulating layer;
gate electrode embedded in the insulating layer;
a dielectric deposition-prohibiting layer formed on a surface of the insulating layer surrounding the gate electrode;
a gate dielectric layer selectively formed on the gate electrode, wherein the gate dielectric layer comprises a first dielectric material;
a channel structure comprising a carbon nanostructure disposed on the gate dielectric layer;
a passivation layer selectively formed on the gate dielectric layer, covering a portion of the channel structure that is disposed on the gate dielectric layer, wherein the passivation layer comprises a second dielectric material; and
source and drain contacts formed on opposing sides of the passivation layer in contact with the channel structure,
wherein the dielectric deposition-prohibiting layer comprises a material that prevents chemical reactive deposition of the first and second dielectric materials on top of exposed portions of the dielectric deposition-prohibiting layer surrounding the gate electrode when the gate dielectric layer and passivation layer are selectively formed by the chemical reactive deposition of the first and second dielectric materials.
2. The device of claim 1 , wherein the dielectric deposition-prohibiting layer comprises a graphene layer.
3. The device of claim 1 , wherein the dielectric deposition-prohibiting layer comprises a molecular self-assembled monolayer.
4. The device of claim 1 , wherein the dielectric deposition-prohibiting layer comprises a hydrophobic monolayer.
5. The device of claim 1 , wherein the carbon nanostructure comprises a carbon nanotube.
6. The device of claim 1 , wherein the passivation layer has sloped sidewalls.
7. The device of claim 1 , wherein the channel structure comprises extended portions that extend past opposing sides of the gate dielectric layer and gate electrode.
8. The device of claim 7 , wherein the extended portions of the channel structure are embedded in the source and drain contacts.
9. An integrated circuit, comprising a substrate, and a transistor device formed on the substrate, wherein the transistor device comprises:
an insulating layer;
gate electrode embedded in the insulating layer;
a dielectric deposition-prohibiting layer formed on a surface of the insulating layer surrounding the gate electrode;
a gate dielectric layer selectively formed on the gate electrode, wherein the gate dielectric layer comprises a first dielectric material;
a channel structure comprising a carbon nanostructure disposed on the gate dielectric layer;
a passivation layer selectively formed on the gate dielectric layer, covering a portion of the channel structure that is disposed on the gate dielectric layer, wherein the passivation layer comprises a second dielectric material; and
source and drain contacts formed on opposing sides of the passivation layer in contact with the channel structure,
wherein the dielectric deposition-prohibiting layer comprises a material that prevents chemical reactive deposition of the first and second dielectric materials on top of exposed portions of the dielectric deposition-prohibiting layer surrounding the gate electrode when the gate dielectric layer and passivation layer are selectively formed by the chemical reactive deposition of the first and second dielectric materials.
10. The integrated circuit of claim 9 , wherein the dielectric deposition-prohibiting layer comprises a graphene layer.
11. The integrated circuit of claim 9 , wherein the dielectric deposition-prohibiting layer comprises a molecular self-assembled monolayer.
12. The integrated circuit of claim 9 , wherein the dielectric deposition-prohibiting layer comprises a hydrophobic monolayer.
13. The integrated circuit of claim 9 , wherein the carbon nanostructure comprises a carbon nanotube.
14. The integrated circuit of claim 9 , wherein the passivation layer has sloped sidewalls.
15. The integrated circuit of claim 9 , wherein the channel structure comprises extended portions that extend past opposing sides of the gate dielectric layer and gate electrode.
16. The integrated circuit of claim 15 , wherein the extended portions of the channel structure are embedded in the source and drain contacts.
17. The device of claim 1 , wherein the first dielectric material and the second dielectric material are different dielectric materials.
18. The device of claim 1 , wherein the first dielectric material and the second dielectric material are the same dielectric materials.
19. The integrated circuit of claim 9 , wherein the first dielectric material and the second dielectric material are different dielectric materials.
20. The integrated circuit of claim 9 , wherein the first dielectric material and the second dielectric material are the same dielectric materials.