Inductive load power switching circuits
Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.
1. A power-factor correction circuit, comprising:
a first switching device comprising a first channel;
an inductive load;
a capacitor; and
a second switching device comprising a second channel; wherein
the first switching device is connected to a node between the inductive load and a floating gate drive circuit, the second switching device is configured to be connected to the floating gate drive circuit, and the second switching device is between the inductive load and the capacitor; and
the power-factor correction circuit is configured such that in a first mode of operation the second switching device blocks a voltage applied across the second switching device in a first direction, in a second mode of operation a substantial current flows through the second channel when a voltage is applied across the second switching device in a second direction and a gate of the second switching device is biased below a threshold voltage of the second switching device, and in a third mode of operation a substantial current flows through the second channel when a voltage is applied across the second switching device in the second direction and the gate of the second switching device is biased above the threshold voltage of the second switching device.
2. The power-factor correction circuit of claim 1 , wherein the first switching device comprises a III-N HEMT.
3. The power-factor correction circuit of claim 1 , wherein the second switching device comprises a III-N HEMT.
4. The power-factor correction circuit of claim 1 , wherein the second switching device comprises a high-voltage depletion mode device and a low-voltage enhancement mode device.
5. A power-factor correction circuit, comprising:
a first switching device comprising a first channel;
an inductive load;
a capacitor; and
a second switching device comprising a second channel; wherein
the first switching device is connected to a node between the inductive load and a floating gate drive circuit, the second switching device is configured to be connected to the floating gate drive circuit, and the second switching device is between the inductive load and the capacitor; and
the power-factor correction circuit is configured such that when a gate of the first switching device is biased higher than a threshold voltage of the first switching device, a gate of the second switching device is biased lower than a threshold voltage of the second switching device, and voltage at a node between the second switching device and the capacitor is sufficiently high to keep the second switching device in a blocking mode, current passes through the inductive load and through the first switching device.
6. A method of operating a power-factor correction circuit, the power-factor correction circuit comprising:
a first switching device comprising a first channel;
an inductive load;
a capacitor; and
a second switching device comprising a second channel; wherein
the first switching device is connected to a node between the inductive load and a floating gate drive circuit, the second switching device is configured to be connected to the floating gate drive circuit, and the second switching device is between the inductive load and the capacitor; the method comprising:
at a first time, biasing a gate of the first switching device higher than a threshold voltage of the first switching device and biasing a gate of the second switching device lower than a threshold voltage of the second switching device, allowing current to flow through the first switching device;
at a second time following the first time, changing a bias on the gate of the first switching device to be lower than the threshold voltage of the first switching device, causing the first switching device to operate in blocking mode and the second switching device to operate in diode mode, allowing current to flow through the second channel of the second switching device; and
at a third time following the second time, changing a bias on the gate of the second switching device to be higher than the threshold voltage of the second switching device, wherein following the third time current continues to flow through the second channel of the second switching device.
7. The method of claim 6 , wherein changing the bias at the third time reduces conduction loss in comparison to switch operation between the second time and the third time.
8. The method of claim 6 , further comprising:
sensing a load current passing through the inductive load; and
when the load current approaches zero, changing the bias on the gate of the second switching device from a voltage higher than the threshold voltage of the second switching device to a voltage lower than the threshold voltage of the second switching device.
9. The method of claim 6 , further comprising:
sensing a load current passing through the inductive load; and
when the load current approaches zero, switching the second switching device from on to off and switching the first switching device from off to on.
10. A power-factor correction circuit, comprising:
a first switching device comprising a first channel;
an inductive load;
a capacitor; and
a second switching device comprising a second channel; wherein
the first switching device is connected to a node between the inductive load and a floating gate drive circuit, the second switching device is configured to be connected to the floating gate drive circuit, and the second switching device is between the inductive load and the capacitor; and
the first switching device or the second switching device comprises a high-voltage depletion mode device and a low-voltage enhancement mode device.
11. A power-factor correction circuit, comprising:
a first switching device comprising a first channel;
an inductive load;
a capacitor; and
a second switching device comprising a gate and a second channel; wherein
the first switching device is connected to a node between the inductive load and the second switching device, and the second switching device is between the inductive load and the capacitor; and
the first switching device or the second switching device comprises a high-voltage depletion mode device and a low-voltage enhancement mode device.
12. A power-factor correction circuit, comprising:
a first switching device comprising a first channel;
an inductive load;
a capacitor; and
a second switching device comprising a gate and a second channel; wherein
the first switching device is connected to a node between the inductive load and the second switching device, and the second switching device is between the inductive load and the capacitor; and
the power-factor correction circuit is configured such that in a first mode of operation the second switching device blocks a voltage applied across the second switching device in a first direction, in a second mode of operation a substantial current flows through the second channel when a voltage is applied across the second switching device in a second direction and a gate of the second switching device is biased below a threshold voltage of the second switching device, and in a third mode of operation a substantial current flows through the second channel when a voltage is applied across the second switching device in the second direction and the gate of the second switching device is biased above the threshold voltage of the second switching device.
13. The power-factor correction circuit of claim 12 , wherein the second switching device is configured to be connected to a gate drive circuit.
14. The power-factor correction circuit of claim 12 , wherein the first and second switching devices comprise III-N HEMTs.
15. The power-factor correction circuit of claim 12 , wherein conduction losses in the circuit are reduced in the third mode of operation as compared to the second mode of operation.
16. A power-factor correction circuit, comprising:
a switching device comprising a first channel;
an inductive load;
a capacitor; and
a device comprising a transistor having a second channel; wherein
the switching device is connected to a node between the inductive load and the device, and the device is between the inductive load and the capacitor; and
the power-factor correction circuit is configured such that in a first mode of operation substantial current flows through the second channel when voltage is applied across the device in a first direction and a gate of the transistor is biased below a threshold voltage of the transistor, and in a second mode of operation substantial current flows through the second channel when voltage is applied across the device in the first direction and the gate of the transistor is biased above the threshold voltage of the transistor.
17. The power-factor correction circuit of claim 16 , wherein the transistor is a III-N HEMT.
18. The power-factor correction circuit of claim 16 , wherein the power-factor correction circuit is configured such that in a third mode of operation the device blocks a voltage applied across the device in a second direction.
19. The power-factor correction circuit of claim 16 , wherein conduction losses in the circuit are reduced in the second mode of operation as compared to the first mode of operation.
20. The power-factor correction circuit of claim 16 , wherein the transistor is a high-voltage depletion mode transistor, and the device further comprises a low-voltage enhancement mode transistor.
21. A method of operating a circuit comprising an inductive load, a first switching device, and a second switching device, the method comprising:
at a first time, biasing a gate of the first switching device higher than a threshold voltage of the first switching device and biasing a gate of the second switching device lower than a threshold voltage of the second switching device, allowing current to flow through the first switching device;
at a second time following the first time, changing a bias on the gate of the first switching device to be lower than the threshold voltage of the first switching device, causing the first switching device to operate in blocking mode and the second switching device to operate in diode mode, allowing current to flow through a channel of the second switching device; and
at a third time following the second time, changing a bias on the gate of the second switching device to be higher than the threshold voltage of the second switching device, wherein following the third time current continues to flow through the channel of the second switching device.
22. The method of claim 21 , wherein the second switching device comprises a high-voltage depletion mode transistor and a low-voltage enhancement mode transistor.
23. The method of claim 22 , wherein the high-voltage depletion mode transistor comprises a III-N HEMT.
24. The method of claim 23 , wherein the low-voltage enhancement mode transistor comprises a Si MOS device or a III-N HEMT.
25. The method of claim 21 , wherein the second switching device comprises a III-Nitride enhancement mode transistor.
26. The method of claim 21 , wherein the circuit comprises a power-factor correction circuit.
27. The method of claim 21 , wherein the first switching device is connected to a node between the inductive load and the second switching device.
28. The method of claim 27 , the circuit further comprising a capacitor, wherein the second switching device is between the inductive load and the capacitor.