Stress engineered multi-layers for integration of CMOS and Si nanophotonics

1. A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device comprising:

depositing a first silicon nitride layer having a first stress property over an active region of the photonic device, the first silicon nitride layer in direct contact with opposing sidewalls of the active region;

depositing an oxide layer having a fifth stress property over the deposited first silicon nitride layer; and

depositing a second silicon nitride layer having a second stress property over the oxide layer,

wherein the deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device, wherein the deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer comprise graded stress properties, the oxide layer including a larger stress than the first silicon nitride layer and the second silicon nitride layer having a larger stress than the oxide layer.

2. The method of claim 1 , wherein the first stress property associated with the first silicon nitride layer comprises a stress value in the range of about −1000 to 1000 Mega Pascal.

3. The method of claim 2 , wherein the fifth stress property associated with the oxide layer comprises a stress value in the range of about −1000 to 1000 Mega Pascal.

4. The method of claim 3 , wherein the second stress property associated with the second silicon nitride layer comprises a stress value in the range of about 0 to −2000 Mega Pascal.

5. The method of claim 1 , further comprising:

depositing a third silicon nitride layer having a third stress property over the second silicon nitride layer,

wherein the deposited first silicon nitride layer, the oxide layer, the second silicon nitride layer, and the third silicon nitride layer encapsulate the photonic device.

6. The method of claim 5 , wherein the third stress property associated with the third silicon nitride layer comprises a stress value in the range of about 0 to 2000 Mega Pascal.

7. The method of claim 1 , wherein the first silicon nitride layer includes a thickness of about 100-1000 Angstroms.

8. The method of claim 1 , wherein the oxide layer includes a thickness of about 100-2000 Angstroms.

9. The method of claim 1 , wherein the second silicon nitride layer includes a thickness of about 500-3000 Angstroms.

10. The method of claim 5 , wherein the third silicon nitride layer includes a thickness of about 500-2000 Angstroms.

11. The method of claim 1 , wherein the first silicon nitride layer, the oxide layer, and the second silicon nitride layer cover the CMOS device.

12. The method of claim 11 , wherein the first silicon nitride layer, the oxide layer, and the second silicon nitride layer provide stress to both the photonic device and the CMOS device, the CMOS device located adjacent to the photonic device, the provided stress varying one or more optical properties of the photonic device and varying one or more electrical properties of the CMOS device.

13. The method of claim 1 , further comprising:

depositing a fourth silicon nitride layer having a fourth stress property over the second silicon nitride layer and the CMOS device, wherein the fourth silicon nitride layer applies stress to the CMOS device.

14. The method of claim 13 , wherein the fourth stress property associated with the fourth silicon nitride layer comprises a stress value in the range of about −2000 to 2000 Mega Pascal.

15. The method of claim 5 , further comprising:

depositing a fourth silicon nitride layer having a fourth stress property over the third silicon nitride layer and the CMOS device, wherein the fourth silicon nitride layer applies stress to the CMOS device.

16. The method of claim 1 , wherein:

the CMOS device comprises an FET transistor having source/drain regions; and

the photonic device comprises a photodetector having a germanium active region.

17. The method of claim 16 , further comprising:

thermally annealing the integrated photonic device for both simultaneously crystallizing the germanium active region and activating implanted dopant material in the source/drain regions, wherein during the crystallization, germanium material from the germanium active region remains encapsulated by the first silicon nitride layer, the oxide layer, and the second silicon nitride layer.

18. The method of claim 17 , wherein the thermally annealing of the integrated photonic device comprises applying a CMOS spike anneal process having a temperature of about 950-1100° C. for a period of less than one second and a temperature ramp of 50° C. per second.