Low cost and high performance bonding of wafer to interposer and method of forming vias and circuits
View Patent ↗A low cost and high performance method for bonding a wafer to an interposer is provided. The technology provides designs and metallization techniques for through via glass applications that is thermal coefficient expansion matched to the glass or synthetic fused quartz substrates. An off-the-shelf glass, such as borosilicate based or Fused Synthetic Quartz, is used with a thick film Cu or Ag and/or a Sodium Ion Enriched (SIE) coating or glass, which may be applied or fired onto the substrate or wafer. Polymer based coatings can be applied in a sequential build-up process for purposes of redistribution of signals from a silicon integrated circuit to the opposite side of the substrate or wafer. Additionally, metallizations can be applied on top of the polymers and patterned to create a multilayer circuit.
1. A method for forming a semiconductor device, comprising:
applying a sodium ion enriched glass on a surface of a substrate to form a sodium ion enriched glass layer on the substrate;
subsequently creating a via in the sodium-ion enriched glass layer of the substrate;
subsequently applying a thick film into the via of the sodium ion enriched glass layer to form the semiconductor device, wherein the via terminates at the surface of the substrate such that the film is touching the surface of the substrate; and
subsequently applying an additional sodium ion enriched glass to an outer surface of the semiconductor device to seal the via.
2. The method of claim 1 , wherein the substrate is borosilicate glass or fused synthetic quartz.
3. The method of claim 1 , wherein the thick film is a copper thick film sintered at 650 C or 850 C.
4. The method of claim 1 , wherein the thick film is a silver thick film sintered at 850 C and having less than 5% shrinkage.
5. The method of claim 1 , wherein a surface of the sodium ion enriched glass layer is processed using a technique selected from a group consisting of:
a. chemically laser etching;
b. mechanically laser etching;
c. plating;
d. soldering; and
e. wire-bonding.
6. The method of claim 1 , further comprising attaching interconnects to the thick film.
7. The method of claim 1 , further comprising spin coating, screen printing, or depositing dielectrics or metal layers to create a route distribution or micro-via.
8. The method of claim 1 , further comprising attaching the semiconductor device to a multi-layer ceramic or a printed wiring board (PWB) to form a system in a chip.
9. The method of claim 8 , wherein the system in a chip implements a digital processing, radio frequency and analog processing, power source or memory storage component.
10. The method of claim 8 , wherein the system in a chip is communicatively coupled to a motherboard or a second PWB.