Method and structure for forming a localized SOI finFET
Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins.
1. A semiconductor structure comprising:
a semiconductor substrate;
a first fin disposed on the semiconductor substrate;
an oxide region formed at a base of the first fin; and
a shallow trench isolation region formed adjacent to, and in physical contact with the first fin at the base, wherein the shallow trench isolation region is below a level of a top of the first fin; and further comprising a gate dielectric layer disposed over the first fin, wherein the first fin comprises an oxide region at the base of the first fin, wherein the oxide region has a V-shaped profile.
2. The structure of claim 1 , further comprising a gate region disposed over the gate dielectric layer.
3. The structure of claim 2 , wherein the gate dielectric layer is comprised of hafnium oxide.
4. The structure of claim 2 , wherein the gate region is comprised of polysilicon.
5. The structure of claim 2 , wherein the gate region is comprised of metal.
6. The structure of claim 1 , wherein the shallow trench isolation region is comprised of silicon oxide.
7. The structure of claim 1 , wherein the shallow trench isolation region has a height ranging from about 0.2 times the height of the first fin to about 2 times the height of the first fin.
8. The structure of claim 1 , further comprising a second fin, wherein the second fin has a physical height identical to the physical height of the first fin, and wherein the second fin has an electrical height that is less than the electrical height of the first fin.
9. The structure of claim 8 , wherein the first fin and second fin are coplanar at the top of each fin.
10. The structure of claim 1 , wherein the gate dielectric layer has a thickness ranging from about 5 angstroms to about 20 angstroms.
11. The structure of claim 8 , wherein the first fin has an electrical fin height ranging from about 70 nanometers to about 150 nanometers, and wherein the second fin has an electrical fin height ranging from about 40 nanometers to about 120 nanometers.