Lateral GaN JFET with vertical drift region
View Patent ↗A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.
1. A semiconductor device comprising:
a III-nitride substrate having a first conductivity type;
a first III-nitride epitaxial layer, having the first conductivity type, in physical contact with the III-nitride substrate;
a blocking layer in direct contact with the first III-nitride epitaxial layer of the first conductivity type and having at least one opening;
a second III-nitride epitaxial layer, having the first conductivity type, and in direct contact with:
the blocking layer, and
the first III-nitride epitaxial layer through the at least one opening in the blocking layer;
a third III-nitride epitaxial layer, having a second conductivity type, and in direct contact with the second III-nitride epitaxial layer such that at least a portion of the second III-nitride epitaxial layer is disposed between at least a portion of the third III-nitride epitaxial layer and at least a portion of the blocking layer to form a channel region; and
a source region in direct contact with the second III-nitride epitaxial layer such that at least a portion of the channel region is disposed between the source region and the at least one opening in the blocking layer; and
a metal structure direct contact with the source region and at least a portion of the blocking layer, the metal structure forming an ohmic contact with the source region.
2. The semiconductor device of claim 1 wherein the source region comprises an implanted region of the second III-nitride epitaxial layer.
3. The semiconductor device of claim 1 further comprising a metal layer in direct contact with the third III-nitride epitaxial layer.
4. The semiconductor device of claim 1 further comprising a metal layer in direct contact with the III-nitride substrate.
5. The semiconductor device of claim 1 wherein:
the blocking layer includes a plurality of openings;
the second III-nitride epitaxial layer is in direct contact with the first III-nitride epitaxial layer through each of the plurality of openings in the blocking layer; and
the source region is in direct contact with the second III-nitride epitaxial layer such that, for each of the plurality of openings in the blocking layer, a respective channel region is disposed between the source region and the opening in the blocking layer.
6. The semiconductor device of claim 1 wherein the blocking layer comprises III-nitride epitaxial structure, having the second conductivity type.
7. A gallium nitride (GaN)-based junction field-effect transistor (JFET) comprising:
a GaN drain region having a top surface extending in a lateral dimension;
a source region;
a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region;
a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region; and
a GaN gate region of a second conductivity type in physical contact with the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region; and
a metal structure forming an ohmic contact with the source region and at least a portion of the blocking layer.
8. The GaN-based JFET of claim 7 further comprising a metal layer in direct contact with the GaN gate region.
9. The GaN-based JFET of claim 7 wherein the blocking layer comprises a GaN epitaxial structure of the second conductivity type.