Power-scalable skew compensation in source-synchronous parallel interfaces
A parallel receiver interface includes a plurality of parallel data receivers, each receiver receiving input data. A clock receiver is configured to receive a forwarded clock. A phase interpolator has an input coupled to the output of the clock receiver and has an output coupled to each of the parallel receivers. Parallel clock delay elements are within each of the parallel data receivers, each clock delay element configured to provide varying amounts of clock phase adjustment. Inputs of a multiplexer circuit within each of the parallel data receivers are coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver. An output of the multiplexer circuit is coupled to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.
1. A parallel, receiver interface comprising:
a plurality of parallel data receivers, each parallel data receiver being configured to receive input data;
a clock receiver configured to receive a forwarded clock;
a phase interpolator, the input of which is coupled to the output of the dock receiver, and the output of which is coupled to each of the parallel receivers;
multiple parallel clock delay elements within each of the parallel data receivers, the multiple parallel clock delay elements including a clock delay element having no phase adjustment capabilities, a clock delay element having phase adjustment capabilities for providing fractional unit interval deskew, and a clock delay element providing 360° phase adjustment capabilities; and
a multiplexer circuit within each of the parallel data receivers, inputs of the multiplexer circuit being coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver, and an output of the multiplexer circuit being coupled directly to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.
2. The parallel receiver interface of claim 1 , wherein a bypass path is provided for the phase interpolator.
3. The parallel receiver interface of claim 1 , wherein parallel clock delay elements not selected by the multiplexer operate in a reduced power state.
4. The parallel receiver interface of claim 1 , wherein one of the parallel clock delay elements within each parallel data receiver is programmable.
5. The parallel receiver interface of claim 1 , wherein one of the parallel clock delay elements within each parallel data receiver is not programmable.
6. The parallel receiver interface of claim 1 , wherein one of the parallel clock delay elements within each parallel data receiver is configured to provide 360° of clock phase adjustment.
7. The parallel receiver interface of claim 1 , wherein multiple clock phases are provided to the clock receiver when selectively enabling at least one clock delay path.
8. A method for skew compensation for source-synchronous parallel interface receiver circuitry comprising:
providing a plurality of independent parallel delay paths for each receiver, wherein each delay path has a different total delay range for clock skew compensation;
providing each receiver with a sampler circuit for capturing data;
providing a multiplexer in each receiver, the multiplexer responsive to the output of each of the independent parallel delay paths and directly coupled to the sampler circuit; and
selectively enabling at least one desired delay path to delay a clock signal input to the source-synchronous parallel interface receiver circuitry and provide a desired clock skew compensation,
wherein providing a plurality of independent delay paths comprises providing:
a delay element having no phase adjustment capabilities;
a delay element having phase adjustment capabilities for providing fractional unit interval deskew; and
a delay element providing 360° phase adjustment capabilities.
9. The method of claim 8 , further comprising bypassing and/or powering down at least one non-desired delay path to reduce power consumption.
10. The method of claim 9 , wherein the bypassing and/or powering down is done by asserting a control signal.
11. The method of claim 8 , wherein the selectively enabling is conducted based upon operating environment.
12. The method of claim 11 , wherein the operating environment is a need for deskew.
13. The method of claim 11 , wherein the operating environment is a need for phase adjustment.
14. The method of claim 8 , further comprising providing multiple clock phases to the receiver when selectively enabling at least one clock delay path.
15. A source-synchronous parallel interface comprising:
a plurality of multiple parallel delay elements;
a sampler circuit for capturing data;
a multiplexer configured to receive the output of each of the multiple parallel delay elements, the multiplexer output being directly coupled to the sampler circuit; and
at least one controller for selectively enabling at least one of the delay elements to delay a clock signal input to the source-synchronous parallel interface such that clock skew is compensated,
wherein the multiple parallel delay elements comprise:
a delay element having no phase adjustment capabilities;
a delay element having phase adjustment capabilities for providing fractional unit interval deskew; and
a delay element providing 360° phase adjustment capabilities.