Method to form solder alloy deposits on substrates

1. A method of forming a solder alloy deposit on a substrate comprising the following steps:

i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area,

ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area,

iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a metal seed layer on the substrate surface,

iv) form a resist layer on the metal seed layer and create openings in the resist layer which expose the solder mask openings and the at least one contact area,

v) electroplate a first solder material layer consisting of pure tin onto the metal seed layer,

vi) electroplate a second solder material layer consisting of a tin-silver alloy onto the first solder material layer,

vii) remove the resist layer and etch away an amount of the metal seed layer sufficient to remove the metal seed layer from the solder mask layer area leaving two stacked solder material layers on the at least one contact area,

viii) reflow the substrate and thereby form a solder alloy deposit from the metal seed layer, the first solder material layer and the second solder material layer,

wherein the composition of the solder alloy deposit is controlled by the volumes of the metal seed layer, the first solder material layer and the second solder material layer and their respective elemental compositions, and

wherein the solder alloy deposit contains more than 50 wt.-% of tin, 1 to 6 wt.-% of silver and 0.05 to 2 wt.-% of copper.

2. The method according to claim 1 , wherein the metal seed layer is selected from the group consisting of copper, tin, cobalt, nickel, silver, tin-lead alloy, copper-nickel alloy, copper-chromium alloy, copper-ruthenium alloy, copper-rhodium alloy, copper-silver alloy, copper-iridium alloy, copper-palladium alloy, copper-platinum alloy, copper-gold alloy, copper-rare earth alloy, copper-nickel-silver alloy, copper-nickel-rare earth metal alloy, copper/tin bi-layer, chromium/copper-chromium alloy/copper multilayer and nickel/tin/copper multilayer.

3. The method according to claim 1 wherein the metal seed layer is selected from the group consisting of copper, copper-nickel alloy, copper-ruthenium alloy and copper-rhodium alloy.

4. The method according to claim 1 wherein the solder alloy deposit is selected from the group consisting of tin-silver-copper alloys and tin-silver-copper-nickel alloys.

5. The method according to claim 1 wherein the substrate is a printed circuit board, an IC substrate or an interposer.

6. The method according to claim 2 wherein the seed layer is selected from the group consisting of copper, copper-nickel alloy, copper-ruthenium alloy and copper-rhodium alloy.

7. The method according to claim 2 wherein the solder alloy deposit is selected from the group consisting of tin-silver-copper alloys and tin-silver-copper-nickel alloys.

8. The method according to claim 3 wherein the solder alloy deposit is selected from the group consisting of tin-silver-copper alloys and tin-silver-copper-nickel alloys.

9. The method according to claim 2 wherein the substrate is a printed circuit board, an IC substrate or an interposer.

10. The method according to claim 3 wherein the substrate is a printed circuit board, an IC substrate or an interposer.

11. The method according to claim 4 wherein the substrate is a printed circuit board, an IC substrate or an interposer.