Double sidewall image transfer process

1. A method comprising:

forming a hardmask on a substrate;

providing first and second mandrels on the hardmask having first and second widths, respectively, wherein the first and second widths are different;

providing a first spacer on each side of each of the first and second mandrels;

removing the first and second mandrels;

providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers;

removing the first spacers;

etching, after removal of the first spacers, the hardmask using the second spacers as a mask; and

generating a plurality of fins by etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask,

wherein the fins have a variable fin pitch less than 40 nm.

2. The method according to claim 1 , the method further comprising:

providing the second mandrel on the hardmask at a distance from the first mandrel, the distance exceeding the first width, second width, or each of the first and second widths.

3. The method according to claim 2 , wherein the first spacers each have a third width being less than the distance, first width, second width, or a combination thereof.

4. The method according to claim 1 , further comprising:

removing the hardmask and the second spacers,

wherein the plurality of fins comprise first, second, third, fourth, fifth, sixth, seventh, and eighth fins, the second fin being between the first and third fin, the third fin being between the second and fourth fins, the fourth fin being between the third and fifth fins, the fifth fin being between the fourth and sixth fins, the sixth fin being between the fifth and seventh fins, and the seventh fin being between the sixth and eighth fins.

5. The method according to claim 4 , comprising:

forming, in the substrate, a first pull-down (PD) transistor, wherein the first fin is formed on the first PD transistor;

forming, in the substrate, a first pass-gate (PG) transistor, wherein the first fin is formed on the first PG transistor;

forming, in the substrate, a first pull-up (PU) transistor, wherein the second fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the third fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the fourth fin is formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the fourth fin is formed on the second PD transistor.

6. The method according to claim 4 , comprising:

forming, in the substrate, a first PD transistor, wherein the first and second fins are formed on the first PD transistor;

forming, in the substrate, a first PG transistor, wherein the first and second fins are formed on the first PG transistor;

forming, in the substrate, a first PU transistor, wherein the third fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the sixth fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the seventh and eighth fins are formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the seventh and eighth fins are formed on the second PD transistor.

7. The method according to claim 6 , wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

8. A method comprising:

forming a hardmask on a substrate;

providing a first mandrel having a first width on the hardmask;

providing a second mandrel having a second width, different from the first width, on the hardmask at a first distance from the first mandrel, the first distance exceeding the first width;

providing a first spacer on each side of each of the first and second mandrels, each of the first spacers having a third width being less than the first and second widths;

removing the first and second mandrels;

providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers, each of the second spacers having a fourth width being less the third width;

removing the first spacers;

etching, after removal of the first spacers, the hardmask using the second spacers as a mask;

etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask, a remaining part of the layer being first, second, third, fourth, fifth, sixth, seventh, and eighth fins, the second fin being between the first and third fin, the third fin being between the second and fourth fins, the fourth fin being between the third and fifth fins, the fifth fin being between the fourth and sixth fins, the sixth fin being between the fifth and seventh fins, and the seventh fin being between the sixth and eighth fins; and

removing the hardmask and the second spacers,

wherein the fins have a variable fin pitch less than 40 nm.

9. The method according to claim 8 , further comprising:

forming, in the substrate, a first pull-down (PD) transistor, wherein the first fin is formed on the first PD transistor;

forming, in the substrate, a first pass-gate (PG) transistor, wherein the first fin is formed on the first PG transistor;

forming, in the substrate, a first pull-up (PU) transistor, wherein the second fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the third fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the fourth fin is formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the fourth fin is formed on the second PD transistor.

10. The method according to claim 8 , further comprising:

forming, in the substrate, a first PD transistor, wherein the first and second fins are formed on the first PD transistor;

forming, in the substrate, a first PG transistor, wherein the first and second fins are formed on the first PG transistor;

forming, in the substrate, a first PU transistor, wherein the third fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the sixth fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the seventh and eighth fins are formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the seventh and eighth fins are formed on the second PD transistor.

11. The method according to claim 10 , wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

12. A method comprising:

forming a hardmask on a substrate;

providing first and second mandrels on the hardmask having first and second widths, respectively, wherein the first and second widths are different;

providing a first spacer on each side of each of the first and second mandrels;

removing the first and second mandrels;

providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers;

removing the first spacers;

etching, after removal of the first spacers, the hardmask using the second spacers as a mask; and

generating a plurality of fins by etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask,

wherein a first fin and a second fin of the plurality of fins are separated by a first distance, the second fin and a third fin of the plurality of fins are separated by a second distance, and the third fin and a fourth fin of the plurality of fins are separated by a third distance, the first distance, the second distance, and the third distance being different from each other.