Silicon-on-insulator heat sink

1. A method of manufacturing a semiconductor structure, comprising:

forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate;

forming a transistor in a second portion of the SOI island; and

electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island,

wherein the doping the first portion of the SOI island comprises an ion implantation process that also dopes an upper portion of the substrate contact.

2. The method of claim 1 , wherein the forming the substrate contact comprises:

etching a trench through the first portion of the SOI island and through a buried insulator layer, wherein the trench extends to or into the substrate; and

filling the trench with a material, wherein a thermal conductivity of the material is greater than a thermal conductivity of the buried insulator layer.

3. The method of claim 1 , wherein the doping the first portion of the SOI island comprises implanting ions of a first type in the first portion of the SOI island.

4. The method of claim 3 , wherein:

the forming the transistor in the second portion of the SOI island comprises forming a source region and a drain region of the transistor in the second portion of the SOI island by implanting ions of a second type in the source region and the drain region; and

the first type of ions is opposite from the second type of ions.

5. The method of claim 4 , further comprising:

forming a block on the first portion of the SOI island and extending over an interface between the first portion of the SOI island and the second portion of the SOI island; and

forming silicide on surfaces of the source region and the drain region that are unmasked by the block.

6. The method of claim 1 , further comprising:

forming a first electrical contact on a source region of the transistor;

forming a second electrical contact on the substrate contact; and

forming a metal layer on and electrically connecting the first electrical contact and the second electrical contact.

7. A method of manufacturing a semiconductor device, comprising:

defining an island in a semiconductor layer of a silicon-on-insulator (SOI) wafer;

forming a trench through the island and an underlying buried insulator layer, wherein the trench extends to or into a substrate under the buried insulator layer;

forming a substrate contact in the trench, wherein the substrate contact comprises a material having a thermal conductivity that is greater than a thermal conductivity of the buried insulator layer;

forming a transistor in the island; and

electrically isolating the substrate contact from the transistor by doping a portion of the island,

wherein the doping the portion of the island comprises an ion implantation process that also dopes an upper portion of the substrate contact.

8. The method of claim 7 , wherein:

the forming the transistor comprises forming a source region and a drain region doped with a first type of impurity in the island;

the electrically isolating the substrate contact from the transistor comprises doping the portion of the island with a second type of impurity; and

the second type of impurity is different than the first type of impurity.

9. The method of claim 7 , wherein the doping the portion of the island comprises doping a region of the island that includes the substrate contact.

10. The method of claim 7 , wherein the doping the portion of the island comprises doping a region of the island that is between the substrate contact and a source region and a drain region of the transistor.

11. The method of claim 7 , wherein the substrate contact is composed of a same material as the island.

12. The method of claim 7 , wherein the substrate contact is composed of silicon.

13. The method of claim 12 , wherein:

the island and the substrate contact form a continuous silicon path extending from a channel of the transistor to the substrate; and

the continuous silicon path maintains electrical isolation of the transistor from the substrate.

14. The method of claim 7 , wherein:

a top surface of the substrate contact is coplanar with a top surface of the island; and

the forming the substrate contact is performed prior to the forming the transistor.

15. The method of claim 1 , wherein the substrate contact is electrically isolated from the transistor such that the substrate contact is prevented from shunting the transistor to the substrate.

16. The method of claim 1 , wherein the substrate contact is composed of a same material as the SOI island.

17. The method of claim 1 , wherein:

the SOI island and the substrate contact form a continuous silicon path extending from a channel of the transistor to the substrate; and

the continuous silicon path maintains electrical isolation of the transistor from the substrate.

18. The method of claim 1 , wherein:

the substrate contact extends through the SOI island;

the substrate contact directly contacts the SOI island;

a top surface of the substrate contact is coplanar with a top surface of the SOI island; and

the forming the substrate contact is performed prior to the forming the transistor.