Granted Patent B2

US 9,009,396 · App. 13/745,686 · Granted Apr 14, 2015

Abstract

Claims (26)

1. A computer system comprising:

a central processing unit (CPU), the CPU including a PCIe controller;

a system memory coupled to the CPU and including flash tables; and

a plurality of physically-addressed solid state disks (SSDs) individually coupled, through a PCIe bus, to the CPU and individually responsive to one or more queued commands, each of the queued commands including a physical address and using the physical addresses to identify the location of data to be stored in or retrieved from at least one of the plurality of physically-addressed SSDs, in blocks, each of the plurality of physically-addressed SSDs being located externally to the CPU, the PCIe controller coupled to the plurality of physically-addressed SSDs, each of the SSDs including a flash subsystem and a non-volatile memory, the flash subsystem including one or more copies of the flash tables and the non-volatile memory having magnetic random access memory (MRAM) that stores updates to the copy of the flash tables, the flash tables including tables used to map logical to physical blocks for identifying the location of data in the physically-addressable SSD,

wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption.

2. The computer system, as recited in claim 1 , wherein the flash subsystem is made of flash NAND memory.

3. The computer system, as recited in claim 1 , wherein the flash subsystem is made of flash NOR memory.

4. The computer system, as recited in claim 1 wherein the flash subsystem includes a flash address space including a MRAM address space mapped to the flash address space wherein access of any one of the spaces of the MRAM address space that are mapped to the flash address space is indicative of access of a space, in the MRAM, corresponding to the mapped MRAM address space.

5. The computer system, as recited in claim 1 , wherein the non-volatile memory includes spin-transfer torque MRAM (STTMRAM).

6. The computer system, as recited in claim 1 , wherein the system memory stores a software driver for managing the flash tables.

7. The computer system, as recited in claim 1 , wherein the physically-addressable SSD includes a CPU sub-system.

8. The computer system, as recited in claim 1 , wherein the CPU sub-system is operable to use a flag indicative of accessing the MRAM or the flash sub-system.

9. The computer system, as recited in claim 1 , wherein the physical addresses identifying the at least one of the plurality of physically-addressed SSDs are identical to addresses in read or write commands.

10. A computer system comprising:

a plurality of physically-addressed solid state disks (SSDs) individually coupled, through a PCIe bus, to the CPU and individually responsive to one or more queued commands, each of the queued commands including a physical address, the queued commands using the physical addresses to identify the location of user data to be stored in or retrieved from at least one of the plurality of physically-addressed SSDs, in blocks, each of the plurality of physically-addressed SSDs being located externally to the CPU, the PCIe controller coupled to the plurality of physically-addressed SSDs, each of the physically-addressed SSDs having associated therewith physical addresses provided by the CPU; and

a system memory coupled to the CPU, the system memory including flash tables used to manage blocks in the physically addressed SSD, the flash tables including tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD,

the physically-addressable SSD including a non-volatile memory and a flash subsystem that includes flash memory configured to save snapshots of the flash tables including a previous version of the flash tables and a current version of the flash tables under the direction of the CPU, the non-volatile memory including a magnetic random access memory (MRAM) that stores changes to the flash tables beyond the snapshots of the flash tables under the direction of the CPU, wherein either the previous or the current version of the snapshot of the flash tables and the stored changes are used to reconstruct the flash tables upon power interruption, further wherein the PCIe controller is operable to use a flag indicative of accessing the MRAM or the flash subsystem.

11. The computer system, as recited in claim 10 , wherein the flash subsystem is made of flash NAND memory.

12. The computer system, as recited in claim 10 , wherein the flash subsystem is made of flash NOR memory.

13. The computer system, as recited in claim 10 , wherein the MRAM is spin-transfer torque MRAM (STTMRAM).

14. The computer system, as recited in claim 10 , wherein system memory is configured to store a software driver for managing the flash tables.

15. The computer system, as recited in claim 14 , wherein the flash subsystem includes a flash address space including a MRAM address space mapped to flash address space wherein access of any one of the spaces of the MRAM address space mapped to flash address space is indicative of access of a corresponding space in the MRAM.

16. The computer system, as recited in claim 10 , wherein the CPU includes a controller coupled to the physically-addressable SSD.

17. The computer system, as recited in claim 10 , wherein the physically-addressable SSD includes a CPU sub-system.

18. The computer system, as recited in claim 17 , wherein the CPU sub-system is operable to use a flag indicative of accessing the MRAM or the flash sub-system.

19. The computer system, as recited in claim 10 , wherein the physical addresses identifying the at least one of the plurality of physically-addressed SSDs are identical to addresses in read or write commands.

Assignments (6)