IP Library Granted Patent US 8,580,621
Granted Patent B2
US 8,580,621 · App. 13/752,524 · Granted Nov 12, 2013

Solder interconnect by addition of copper

Inventors: Mark A. Bachman (Sinking Spring, PA); John W. Osenbach (Kutztown, PA); Kishor V. Desai (Fremont, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,580,621
App. No.
13/752,524
Granted
Nov 12, 2013
Kind
B2
Abstract

A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Claims (23)

1. A method of forming an electronic device, comprising:

providing an electronic device substrate having a solder bump located thereover;

forming a copper-containing layer on said solder bump; and

placing said copper-containing layer in contact with a nickel-containing layer while causing said solder bump to melt.

2. The method of claim 1 , wherein said electronic device substrate is an integrated circuit substrate.

3. The method of claim 1 , wherein said electronic device substrate is an electronic device package substrate.

4. The method of claim 1 , wherein said copper-containing layer has a copper mass in a range of about 0.5% to about 4% of a mass of said solder bump.

5. The method of claim 1 , further comprising melting said solder bump, thereby forming a (Ni,Cu)/Sn intermetallic compound region between said solder bump and a solder bump pad.

6. A method of forming an electronic device, comprising:

providing an electronic device substrate having a solder bump located thereover; and

forming a copper-containing layer on said solder bump, wherein said copper-containing layer is formed by electroplating.

7. A method of forming an electronic device, comprising:

providing an electronic device substrate having a solder bump located thereover; and

forming a copper-containing layer on said solder bump, wherein said copper-containing layer is formed from a copper paste.

8. A method of forming an electronic device, comprising:

providing an electronic device substrate having a bump pad located thereover, said bump pad including side surfaces and a planar top surface comprising Al or Cu;

providing a nickel-containing layer located on and forming an interface with said top and side surfaces of said solder bump pad;

providing a solder bump located over said nickel-containing layer, wherein said solder bump is composed of an alloy of silver, tin and copper; and

forming an intermetallic compound layer located between and in contact with said nickel-containing layer and said solder bump, wherein said intermetallic compound layer includes:

a first intermetallic compound sublayer adjacent to said solder bump, said first intermetallic compound sublayer composed of an alloy of nickel, copper and tin, and

a second intermetallic compound sublayer adjacent to said first intermetallic compound sublayer and said nickel-containing layer, said second intermetallic compound sublayer composed of an alloy of nickel and tin.

9. The method of claim 8 , wherein said nickel-containing layer is an elemental nickel layer.

10. The method of claim 8 , wherein forming said intermetallic compound layer includes melting said a solder bump in contact with a copper-containing layer, wherein said intermetallic compound layer has a concentration of copper in a range of about 55 wt % to about 65 wt %.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2013
From: BACHMAN, MARK A; OSENBACH, JOHN W; DESAL, KISHOR V
To: LSI CORPORATION
Reel/Frame 029711/0063 →
Continuity (2)
Division 12501686 · Jul 13, 2009
Related Publication 20130149857A1 · Jun 13, 2013