Methods for fabricating integrated circuits with improved semiconductor fin structures

1. A method for fabricating integrated circuits comprising:

providing a mandrel layer overlying a semiconductor substrate;

patterning the mandrel layer into mandrel structures;

forming a protective layer between the mandrel structures;

forming spacers around each of the mandrel structures and overlying portions of the protective layer to define exposed regions of the protective layer and covered regions of the protective layer;

etching the exposed regions of the protective layer using the spacers and the mandrel structures as a mask;

removing the spacers from the covered regions of the protective layer, wherein the covered regions of the protective layer form mask segments for etching the semiconductor substrate;

removing the mandrel structures; and

etching the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

2. The method of claim 1 wherein etching the semiconductor substrate exposed between mask segments to form semiconductor fin structures comprises forming recesses between semiconductor fin structures, wherein the recesses have a uniform width.

3. The method of claim 1 wherein the forming a protective layer between the mandrel structures comprises forming a protective layer between the mandrel structures having a substantially planar upper surface, and wherein the covered regions of the protective layer form mask segments having substantially planar upper surfaces.

4. The method of claim 1 wherein forming a protective layer between the mandrel structures comprises:

coating the semiconductor substrate with a flowable material; and

etching the flowable material to form the protective layer between the mandrel structures.

5. The method of claim 1 wherein forming a protective layer between the mandrel structures comprises coating the semiconductor substrate with an organic planarizing layer (OPL) and curing the OPL to form the protective layer between the mandrel structures having a planar upper surface.

6. The method of claim 1 wherein forming spacers around each of the mandrel structures and overlying the protective layer comprises forming each spacer separated from a first adjacent spacer by a first distance and separated from a second adjacent spacer by a second distance equal to the first distance.

7. The method of claim 6 wherein etching the semiconductor substrate exposed between mask segments to form semiconductor fin structures comprises forming semiconductor fin structures separated by the first distance.

8. The method of claim 7 wherein removing the spacers from the covered regions of the protective layer exposes the mask segments having substantially planar upper surfaces.

9. A method for fabricating semiconductor fin structures for integrated circuits comprising:

forming mandrel structures from a mandrel layer overlying a surface of a semiconductor substrate;

forming a layer between the mandrel structures;

forming spacers overlying the layer to define exposed regions of the layer and covered regions of the layer;

etching the exposed regions of the layer, wherein each covered region of the layer forms a mask segment and each mask segment has a planar upper surface substantially parallel to the surface of the semiconductor substrate;

removing the mandrel structures; and

etching the semiconductor substrate between mask segments to form the semiconductor fin structures.

10. The method of claim 9 wherein etching the semiconductor substrate between mask segments to form the semiconductor fin structures comprises etching the semiconductor substrate between mask segments to form the semiconductor fin structures separated by a uniform distance.

11. The method of claim 9 wherein etching the semiconductor substrate between mask segments to form the semiconductor fin structures comprises etching the semiconductor substrate between mask segments to form the semiconductor fin structures having substantially vertical sidewalls.

12. The method of claim 9 further comprising removing the spacers from the covered regions of the layer.

13. The method of claim 12 wherein removing the spacers from the covered regions of the layer exposes the mask segments having substantially planar upper surfaces.

14. The method of claim 9 wherein the forming the layer between the mandrel structures comprises forming a protective layer between the mandrel structures having a substantially planar upper surface.

15. The method of claim 9 wherein forming the layer between the mandrel structures comprises:

coating the semiconductor substrate with a flowable material; and

etching the flowable material to form the layer between the mandrel structures.

16. The method of claim 9 wherein forming the layer between the mandrel structures comprises coating the semiconductor substrate with an organic planarizing layer (OPL) and curing the OPL to form the layer between the mandrel structures having a planar upper surface.

17. The method of claim 9 wherein forming spacers around each of the mandrel structures and overlying the layer comprises forming each spacer separated from a first adjacent spacer by a first distance and separated from a second adjacent spacer by a second distance equal to the first distance.

18. The method of claim 17 wherein etching the semiconductor substrate between mask segments to form the semiconductor fin structures comprises etching the semiconductor substrate between mask segments to form the semiconductor fin structures separated by the first distance.

19. A method for fabricating integrated circuits comprising:

forming mandrel structures overlying a surface of a semiconductor substrate;

coating the semiconductor substrate with an organic planarizing layer (OPL) and curing the OPL to form a protective layer between the mandrel structures;

forming spacers around each of the mandrel structures and overlying portions of the protective layer to define exposed regions of the protective layer and covered regions of the protective layer;

etching the exposed regions of the protective layer using the spacers and the mandrel structures as a mask;

removing the mandrel structures and the spacers, wherein the covered regions of the protective layer form mask segments; and

etching the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

20. The method of claim 19 wherein coating the semiconductor substrate with an organic planarizing layer (OPL) and curing the OPL to form a protective layer between the mandrel structures comprises forming a protective layer having a planar upper surface, and wherein removing the mandrel structures and the spacers forms mask segments having a planar upper surface.