Method and apparatus for DMA transfer with synchronization optimization
A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.
1. A system for optimizing direct memory access (DMA) data transfer from a single source device to a plurality of destination devices on a computer bus, the system comprising:
a first DMA control circuit configured to transfer a payload of data from the source device to a first destination device, the payload of data divided into a plurality of chunks of data;
a second DMA control circuit configured to transfer the payload of data from the source device to a second destination device, and configured to perform a logical operation on the data transferred to the second destination device;
a synchronization controller operatively coupled to the first DMA control circuit and to the second DMA control circuit, and configured to control each DMA control circuit to independently transfer the chunk of data, wherein the synchronization controller is configured to receive a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data; and
the synchronization controller configured to facilitate transfer of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.
2. The system of claim 1 , wherein the payload of data is divided into a plurality of chunks of data of equal size.
3. The system of claim 2 , wherein the payload of data is divided into one or more chunks of data.
4. The system of claim 1 , wherein the computer bus is a serial data bus.
5. The system of claim 4 , wherein the serial data bus is a PCI Express compatible bus.
6. The system of claim 2 , wherein the payload of data corresponds to a maximum payload size associated with a PCI Express bus protocol.
7. The system of claim 1 , wherein the source device is a memory circuit, a flash memory circuit, a memory interface, or a flash memory interface.
8. The system of claim 1 , wherein the first destination device is a host device or a host interface.
9. The system of claim 1 , wherein the second destination device is buffer into which the transferred data has been processed in accordance with a logical operation.
10. The system of claim 9 , wherein the logical operation is at least one of an XOR operation, an OR operation, a NOR operation, an AND operation, a NAND operation, a parity operation, and a checksum operation.
11. The system of claim 1 , wherein the first DMA control circuit is configured to transfer data at a first data transfer rate, and the second DMA control circuit is configured to transfer data at a second data transfer rate, wherein the first data transfer rate is different than the second data transfer rate.
12. A system for optimizing DMA data transfer on a computer bus, from a single source device to a plurality of destination devices, the system comprising:
a first DMA control circuit configured to transfer data from the source device to a first destination device;
a second DMA control circuit configured to transfer data from the source device to a second destination device, and configured to perform a logical operation on the data transferred to the second destination device;
a synchronization controller operatively coupled to the first DMA control circuit and to the second DMA control circuit, and configured to synchronize transfer of a payload of data from the source device to both the first and second destination devices;
the synchronization controller configured to divide the payload of data into a plurality of chunks of data and control each DMA control circuit to facilitate the transfer of each chunk of data by the respective DMA control circuit;
the synchronization controller configured to initialize each DMA control circuit in an identical manner, and control each DMA control circuit to begin data transfer at the same time such that the first DMA control circuit and the second DMA control circuit transfer the chunk of data without intervention by the synchronization controller, and provide a signals to the synchronization circuit indicating that both DMA control circuits have finished transferring the corresponding chunk of data; and
wherein when both DMA control circuits have finished transferring the corresponding chunk of data, the synchronization controller facilitates transfer of a next chunk of data until all chunks of data of the payload of data have been transferred by the first and second DMA controllers.
13. The system of claim 12 , wherein the computer bus is a serial data bus.
14. The system of claim 13 , wherein the serial data bus is a PCI Express compatible bus.
15. The system of claim 14 , wherein the payload of data corresponds to a maximum payload size associated with a PCI Express bus protocol.
16. The system of claim 12 , wherein the source device is a memory circuit, a flash memory circuit, a memory interface, or a flash memory interface.
17. The system of claim 12 , wherein the first destination device is a host device or a host interface.
18. The system of claim 12 , wherein the second destination device is buffer into which the transferred data has been processed in accordance with a logical operation.
19. The system of claim 18 , wherein the logical operation is at least one of an XOR operation, an OR operation, a NOR operation, an AND operation, a NAND operation, a parity operation, or a checksum operation.
20. The system of claim 12 , wherein the first DMA control circuit is configured to transfer data at a first data transfer rate, and the second DMA control circuit is configured to transfer data at a second data transfer rate, wherein the first data transfer rate is different than the second data transfer rate.
21. The system of claim 12 , wherein the payload of data is divided into one or more chunks of data.
22. A method for optimizing DMA data transfer on a computer bus, from a single source device to a first destination device and a second destination device, the system comprising:
dividing a payload of data into a plurality of chunks of data;
performing a logical operation on the data transferred to the second destination device;
synchronizing, using a synchronizer circuit, a transfer of a payload of data from the source device to both the first and second destination devices by controlling a first DMA control circuit to transfer data from the source device to the first destination device and by controlling a second DMA control circuit to transfer data from the source device to the second destination device;
initializing each DMA control circuit in an identical manner, and directing each DMA control circuit to begin data transfer at the same time such that the first DMA control circuit and the second DMA control circuit transfer the chunk of data;
providing signals to the synchronization circuit indicating that both DMA control circuits have finished transferring the corresponding chunk of data; and
transferring a next chunk of data only when both DMA control circuits have finished transferring the chunk of data, until all chunks of data of the payload of data have been transferred by the first and second DMA controllers.