Methods for isolating portions of a loop of pitch-multiplied material and related structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.
1. A process for forming an integrated circuit, comprising:
providing a plurality of lines on sides of an other plurality of lines, the plurality of lines having first and second opposing ends;
selectively removing the other plurality of lines;
providing a first block of masking material at the first ends of the plurality of lines, the first block of masking material extending across and covering a plurality of the first ends;
providing a second block of masking material at the second ends of the plurality of lines, the second block of masking material extending across and covering a plurality of the second ends;
transferring a pattern formed by the plurality of lines and the first and second blocks of masking material to an underlying substrate, thereby forming lines of semiconductor material interconnected at each end of the lines by blocks of semiconductor material; and
forming connections for connecting the lines of semiconductor material to logic circuitry.
2. The process of claim 1 , wherein providing a plurality of lines on sides of an other plurality of lines comprises:
etching a layer of material over the substrate to form the other plurality of lines; and
subsequently forming the plurality of lines along sidewalls of the lines of the other plurality of lines.
3. The process of claim 2 , wherein the lines of the plurality of lines are alternatingly separated by open volumes and by the lines of the other plurality of lines.
4. The process of claim 3 , wherein the layer of material is a layer of photoresist.
5. The process of claim 2 , wherein subsequently forming the plurality of lines along sidewalls of the other plurality of lines comprises:
blanket depositing a layer of spacer material on the other plurality of lines; and
etching the layer of spacer material to define spacers along the sidewalls of the lines of the other plurality of lines.
6. The process of claim 1 , further comprising:
doping semiconductor regions on opposing sides of portions of the lines of the plurality of lines, thereby forming source/drain regions, the portions proximate the first and second ends and constituting active areas; and
forming transistor gates directly over the active areas.
7. The process of claim 6 , further comprising electrically shunting together the first ends with the transistor gates proximate the first ends, and electrically shunting together the second ends with the transistor gates proximate the second ends.
8. The process of claim 1 , wherein the first block of masking material extends across and contacts all of the first ends of the first and wherein the second block of masking material extends across and contacts all of the second ends.
9. A process for forming an integrated circuit, comprising:
providing a plurality of mandrels overlying a semiconductor substrate;
providing spacers at sidewalls of the mandrels;
selectively removing the mandrels relative to the spacers;
depositing a layer of mask material over the spacers;
patterning the layer of mask material to form first and second laterally-separated blocks of the mask material, the first block contacting a first end of each of the spacers and the second block contacting a second end of each of the spacers;
transferring a first pattern defined by the spacers and the first and second blocks to the semiconductor substrate, thereby defining a plurality of semiconductor lines in the semiconductor substrate; and
forming connections for connecting the semiconductor lines to logic circuitry.
10. The process of claim 9 , wherein providing a plurality of mandrels comprises:
providing a photoresist layer overlying a temporary layer, the temporary layer overlying the semiconductor substrate;
patterning the photoresist layer to form photoresist features; and
trimming the photoresist features, wherein the trimmed photoresist features form the mandrels.
11. The process of claim 10 , wherein providing spacers at sidewalls of the mandrels comprises:
blanket depositing a layer of spacer material over the photoresist features; and
removing the spacer material from horizontal surfaces to define spacers on sidewalls of the photoresist features.
12. The process of claim 9 , wherein transferring the first pattern defined by the spacers and the first and second blocks to the semiconductor substrate comprises:
transferring the first pattern defined by the spacers and the first and second blocks to a hard mask layer disposed between the first and second blocks and the hard mask layer; and
transferring the first pattern from the hard mask layer to the semiconductor substrate.
13. The process of claim 12 , further comprising:
providing one or more additional hard mask layers on a level between the spacers and the hard mask layer; and
etching the first pattern into the one or more additional hard mask layers before transferring the first pattern to the hard mask layer.
14. The process of claim 12 , wherein the hard mask layer is formed of amorphous carbon.
15. The process of claim 9 , wherein depositing a layer of mask material over the spacers comprises depositing a layer of photoresist.
16. A process for forming an integrated circuit, comprising:
providing a plurality of elongated loops of a first mask material overlying a semiconductor substrate;
providing a layer of a second mask material over the elongated loops;
patterning the layer of the second mask material to form an isolated block of the second mask material, the isolated block contacting and substantially localized directly over an end of each of the plurality of elongated loops;
transferring a first pattern defined by the plurality of elongated loops and the isolated block to the semiconductor substrate, thereby defining a plurality of semiconductor lines in the semiconductor substrate; and
forming connections for connecting the semiconductor lines to logic circuitry.
17. The process of claim 16 , further comprising:
subsequently forming a layer of semiconductor material over the semiconductor substrate;
forming an other layer of mask material over the semiconductor material;
patterning the other layer of mask material to form one or more strips of masking material extending across and over semiconductor lines of the plurality of semiconductor lines;
transferring a second pattern defined by the one or more strips of masking material to the layer of semiconductor material to form strips of semiconductor material.
18. The process of claim 17 , further comprising electrically connecting the strips of semiconductor material and substrate features defined by the isolated block of the second mask material.
19. The process of claim 17 , wherein transferring the second pattern defines a gate of a transistor and transferring the first pattern defines a source/drain region of the transistor.
20. The process of claim 17 , wherein transferring the first pattern defines bit lines of a memory device.
21. The process of claim 20 , wherein transferring the second pattern defines word lines of the memory device.
22. The process of claim 17 , wherein the integrated circuit is a flash memory circuit, wherein transferring the first and the second patterns defines floating gate transistors in an array region of the flash memory circuit.
23. The process of claim 16 , wherein transferring a first pattern defined by the plurality of elongated loops and the isolated block to the semiconductor substrate defines features in a periphery region of the flash memory circuit.