Non-volatile storage with read process that reduces disturb

1. A method of reading non-volatile storage, comprising:

performing a first read process, comprising:

applying a first read compare voltage to a first selected data memory cell in a middle of a NAND string, the NAND string is connected to a plurality of word lines for a block, the block includes dummy word lines at ends of the NAND string, the dummy word lines are connected to dummy memory cells that do not store user data,

applying a first set of one or more read pass voltages to one or more unselected data memory cells that are adjacent to the first selected data memory cell,

applying a second set of one or more read pass voltages to multiple unselected data memory cells on the NAND string that are not adjacent to the first selected data memory cell, the second set of one or more read pass voltages are all lower voltages than the first set of one or more read pass voltages, a majority of unselected data memory cells on the NAND string receive the second set of one or more read pass voltages, and

applying a dummy word line voltage to a first dummy word line, the dummy word line voltage is lower in magnitude than the second set of one or more read pass voltages; and

performing a second read process, comprising:

applying a second read compare voltage to a second selected data memory cell at an end of the NAND string, the second selected data memory cell is adjacent to the first dummy word line,

applying a third set of one or more read pass voltages to multiple unselected data memory cells on the NAND string that are not adjacent to the second selected data memory cell,

applying a fourth read pass voltage to an unselected memory cell that is adjacent to the second selected memory cell, the fourth read pass voltage is larger in magnitude than the third set of one or more read pass voltages and the second set of one or more read pass voltages, and

applying a voltage on the first dummy word line that is higher in magnitude than the fourth read pass voltage.

2. The method of claim 1 , wherein:

the first read process further comprises applying a fifth read pass voltage to the data memory cell that is adjacent to the first dummy word line; and

the fifth read pass voltage is lower in magnitude than the first set of one or more read pass voltages and the second set of one or more read pass voltages.

3. The method of claim 1 , wherein:

the third set of one or more read pass voltages is equal to the second set of one or more read pass voltages;

the fourth read pass voltage is equal to the first set of one or more read pass voltages; and

during the second read process, a majority of unselected data memory cells on the NAND string receive the third set of one or more read pass voltages.

4. The method of claim 1 , wherein:

the second read process further comprises applying a fifth read pass voltage to a data memory cell that is at a different end of the NAND string and is adjacent to a second dummy word line; and

the fifth read pass voltage is lower in magnitude than the third set of one or more read pass voltages.

5. The method of claim 1 , wherein:

the first set of one or more read pass voltages includes one read pass voltage; and

the second set of one or more read pass voltages includes one read pass voltage.

6. A non-volatile storage system, comprising:

a plurality of memory cells arranged in a plurality of NAND strings;

a plurality of data word lines connected to the non-volatile storage elements;

a dummy word line at a first end of each of the plurality of NAND strings, the dummy word line is connected to dummy memory cells that do not store user data; and

one or more managing circuits in communication with the data word lines and the dummy word line as well as the non-volatile storage elements to program and read the non-volatile storage elements, the one or more managing circuits perform a first read process to read data from memory cells in a middle region of the NAND strings and perform a second read process to read data from memory cells at an end of the NAND strings adjacent to the dummy word line,

when performing the first read process, the one or more managing circuits apply a first read compare voltage to a first selected word line connected to first selected data memory cells of a plurality of NAND strings, apply a first set of one or more read pass voltages to one or more unselected word lines connected to unselected data memory cells adjacent to the first selected data memory cells, and apply a second set of one or more read pass voltages to multiple unselected word lines connected to unselected data memory cells that are not adjacent to the first selected data memory cells, the second set of one or more read pass voltages are all lower than the first set of one or more read pass voltages,

when performing the second read process, the one or more managing circuits apply a second read compare voltage to a second selected word line connected to second selected data memory cells at the end of the NAND strings, apply a third set of one or more read pass voltages to unselected word lines connected to multiple unselected data memory cells on the NAND strings that are not adjacent to the second selected data memory cells, apply a fourth read pass voltage to an unselected word line connected to unselected memory cells that are adjacent to the second selected memory cells such that the fourth read pass voltage is larger in magnitude than the third set of one or more read pass voltages, and apply a voltage on the dummy word line that is higher in magnitude than the fourth read pass voltage.

7. The non-volatile storage system of claim 6 , wherein:

during the first read process, a majority of the word lines receive the second set of one or more read pass voltages; and

during the second read process, a majority of the word lines receive the third set of one or more read pass voltages.

8. The non-volatile storage system of claim 6 , wherein:

during the first read process the one or more managing circuits apply a fifth read pass voltage to the word line that is connected to memory cells at the end of the NAND strings; and

the fifth read pass voltage is lower in magnitude than the first set of one or more read pass voltages and the second set of one or more read pass voltages.

9. The non-volatile storage system of claim 6 , wherein:

during the second read process the one or more managing circuits apply a fifth read pass voltage to a word line at a different end of the NAND string than the dummy word line; and

the fifth read pass voltage is lower in magnitude than the third set of one or more read pass voltages and the fourth read pass voltage.

10. A method of reading non-volatile storage, comprising:

applying read compare voltages to selected word lines that are connected to selected data memory cells of a plurality of NAND strings, the plurality of NAND strings connected to word lines of a block, the block includes a dummy word line at end of the NAND strings, the dummy word line is connected to dummy memory cells that do not store user data;

applying a first set of one or more read pass voltages to a majority of unselected word lines that are connected to unselected data memory cells of the NAND strings;

applying a first higher read pass voltage to unselected word lines adjacent to selected word lines, the first higher read pass voltage is higher in magnitude than the first set of one or more read pass voltages; and

applying a second higher read pass voltage to the dummy word line when reading data memory cells at an extreme end of the NAND strings, the second higher read pass voltage is higher in magnitude than the first higher read pass voltage.

11. The method of claim 10 , further comprising:

applying an end word line voltage to a word line at an end of the NAND strings, the end word line voltage is lower in magnitude than the first set of one or more read pass voltage.

12. A non-volatile storage system, comprising:

a plurality of data memory cells arranged in a plurality of NAND strings;

a plurality of data word lines connected to the plurality of NAND strings;

a dummy word line at a first end of each of the plurality of NAND strings, the dummy word line is connected to dummy memory cells that do not store user data, the plurality of data word lines include a first data word line adjacent to the dummy word line; and

one or more managing circuits in communication with the data word lines and the dummy word line, the one or more managing circuits apply a first set of one or more read pass voltages to a majority of unselected word lines that are connected to unselected data memory cells of the NAND strings during read processes, the one or more managing circuits apply adjacent read pass voltages to data word lines that are adjacent to selected word lines during read processes, the adjacent read pass voltages are higher in magnitude than the first set of one or more read pass voltages, the one or more managing circuits apply a first dummy word line voltage to the dummy word line during read processes for memory cells on the first data word line and apply a second dummy word line voltage to the dummy word line during read processes for memory cells on data word lines other than the first data word line, the first dummy word line voltage is higher in magnitude than the adjacent read pass voltages, the second dummy word line voltage is lower in magnitude than the a first set of one or more read pass voltages.