IP Library Granted Patent US 8,927,369
Granted Patent B2
US 8,927,369 · App. 13/789,692 · Granted Jan 6, 2015

Method of forming a trench gate MOSFET having a thick bottom oxide

Inventors: Chien-Ling Chan (Hsinchu County, TW); Chi-Hsiang Lee (Hsinchu County, TW)
Assignee: UBIQ Semiconductor Corp.
H01L29/66666H01L29/42368H01L29/66727H01L29/66734H01L29/7813H01L29/41766H01L29/42376
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Quick Facts
Patent No.
US 8,927,369
App. No.
13/789,692
Granted
Jan 6, 2015
Kind
B2
Abstract

A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Claims (30)

1. A method of forming a trench gate MOSFET, comprising:

forming an epitaxial layer with a first conductivity type on a substrate with the first conductivity type;

forming a trench in the epitaxial layer;

conformally forming a first insulating layer and a first conductive layer on surfaces of the epitaxial layer and the trench;

filling up the trench with a second insulating layer;

removing a portion of the first conductive layer to form a second conductive layer below the second insulating layer;

removing the second insulating layer and a portion of the first insulating layer to form a third insulating layer below the second conductive layer;

performing an oxidation process to oxidize the second conductive layer to a fourth insulating layer, wherein a fifth insulating layer is simultaneously formed on the surface of the epitaxial layer and on a sidewall of the trench by the oxidation process;

forming a third conductive layer in the trench;

forming two body layers with a second conductivity type in the epitaxial layer respectively beside the trench; and

forming two doped regions with the first conductivity type in the body layers respectively beside the trench.

2. The method of forming the trench gate MOSFET as recited in claim 1 , wherein a method of forming the second insulating layer comprises:

forming an insulating material layer on the epitaxial layer, and the insulating material layer filling up the trench; and

performing an etching back process to remove a portion of the insulating material layer.

3. The method of forming the trench gate MOSFET as recited in claim 1 , wherein a method of forming the second conductive layer comprises using the second insulating layer as a mask to perform an anisotropic dry etching process.

4. The method of forming the trench gate MOSFET as recited in claim 1 , wherein a method of forming the third insulating layer comprises using the second conductive layer as a mask to perform an anisotropic dry etching process.

5. The method of forming the trench gate MOSFET as recited in claim 1 , wherein the method of forming the third conductive layer comprises:

forming a conductive material layer on the epitaxial layer, and the conductive material layer filling up the trench; and

performing an etching back process to remove a portion of the conductive material layer.

6. The method of forming the trench gate MOSFET as recited in claim 1 , further comprising, after the step of performing the oxidation process and before the step of forming the third conductive layer:

removing the fifth insulating layer and a portion of the fourth insulating layer; and

forming a sixth insulating layer on the surfaces of the epitaxial layer and the trench.

7. The method of forming the trench gate MOSFET as recited in claim 1 , further comprising, after the step of forming the doped regions:

forming a dielectric layer on the third conductive layer and the doped regions;

forming two openings penetrating the dielectric layer and the doped regions; and

forming a fourth conductive layer on the dielectric layer, wherein the fourth conductive layer fills in the openings to be electrically connected to the body layers.

8. The method of forming the trench gate MOSFET as recited in claim 7 , wherein a material of the fourth conductive layer comprises metal.

9. The method of forming the trench gate MOSFET as recited in claim 1 , wherein a material of the first conductive layer comprises undoped polysilicon.

10. The method of forming the trench gate MOSFET as recited in claim 1 , wherein a material of the third conductive layer comprises doped polysilicon.

11. The method of forming the trench gate MOSFET as recited in claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

Assignments (2)
MERGER Recorded Jul 4, 2019
From: UBIQ SEMICONDUCTOR CORP.
To: UPI SEMICONDUCTOR CORP.
Reel/Frame 049668/0484 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2013
From: CHAN, CHIEN-LING; LEE, CHI-HSIANG
To: UBIQ SEMICONDUCTOR CORP.
Reel/Frame 029991/0754 →
Priority Claims (1)
TW 101125348 U · Jul 13, 2012 · national
Continuity (1)
Related Publication 20140017864A1 · Jan 16, 2014