Systems and methods for performing defect detection and data recovery in a memory system

1. A method for performing defect detection and data recovery within a memory system, the method comprising:

in a controller of a memory system coupled to a host device:

receiving a command to write data in a memory of the memory system;

determining a physical location of the memory that is associated with the data write;

writing data associated with the data write to the physical location of the memory;

determining whether a Flash Management Unit Tag cache (“Tag cache”) is full;

in response to determining that the Tag case is not full, storing the physical location of the memory that is associated with the data write in the Tag cache;

in response to determining that the Tag cache is full:

flushing the Tag cache and a plurality of data keep caches;

after flushing the Tag cache and the plurality of data keep caches, storing the physical location of the memory that is associated with the data write in the Tag cache;

identifying an edge wordline associated with an open memory block of the memory;

storing a physical location of the memory that is associated with the edge wordline in the Tag cache; and

updating, based on data stored at the physical location of the memory that is associated with the edge wordline, an XOR sum stored in a data keep cache that is associated with the physical location of the memory that is associated with the edge wordline;

identifying a data keep cache of the plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write;

updating an XOR sum stored in the identified data keep cache based on the data of the data write and the XOR sum that is stored in the identified data keep cache; and

storing the updated XOR sum in the identified data keep cache.

2. The method of claim 1 , wherein the Tag cache comprises a first-in-first-out data cache.

3. The method of claim 1 , wherein the plurality of data keep caches comprises:

a first data keep cache associated with upper pages and even numbered word lines of a die of the memory;

a second data keep cache associated with upper pages and odd numbered word lines of the die of the memory;

a third data keep cache associated with lower pages and even numbered word liens of the die of the memory; and

a fourth data keep cache associated with lower pages and odd numbered word lines of the die of the memory.

4. The method of claim 1 , further comprising:

determining that a failure occurred during the data write;

determining that the physical location of the memory associated with the data write is stored in the Tag cache;

calculating the data associated with the data write based on the XOR sum that is stored in the data keep cache associated with the physical location of the memory that is associated with the data write; and

restoring the data associated with the data write to the physical location of the memory.

5. The method of claim 4 , further comprising:

determining a second physical location of the memory that may have a potential error based on the determined failure at the physical location of the memory;

identifying a second data keep cache of the plurality of data keep caches that is associated with the second physical location of the memory;

calculating data associated with the second physical location of the memory based on an XOR sum that is stored in the second data keep cache;

comparing the calculated data associated with the second physical location of the memory to data that is stored at the second physical location of the memory to determine whether the data that is stored at the second physical location of the memory has been disturbed; and

restoring the data stored at the second physical location of the memory in response to determining that the data stored at the second physical location of the memory has been disturbed.

6. The method of claim 1 , further comprising:

determining a need to erase data stored at the physical location of the memory;

determining whether the physical location of the memory is stored in the Tag cache;

flushing the Tag cache and the plurality of data keep caches in response to determining that the physical location of the memory is stored in the Tag cache; and

erasing data that is stored at the physical location of the memory.

7. The method of claim 1 , further comprising:

determining whether a number of data writes to the physical location of the memory exceeds a threshold; and

disabling the plurality of data keep caches in response to determining that the number of data writes to the physical location of the memory exceeds the threshold.

8. The method of claim 1 , further comprising:

dynamically adjusting a size of the Tag cache or one or more data keep cache of the plurality of data keep caches based on a number of open data block in the storage device.

9. A memory system coupled with a host device, the memory system comprising:

a non-volatile memory; and

a processor in communication with the non-volatile memory and configured to perform defect detection and data recovery within the memory system, the processor configured to:

receive a command to write data in the non-volatile memory;

determine a physical location of the non-volatile memory that is associated with the data write;

write data associated with the data write to the physical location of the non-volatile memory;

determine whether a Flash Management Unit Tag cache (“Tag cache”) is full;

in response to a determination that the Tag case is not full, store the physical location of the non-volatile memory that is associated with the data write in the Tag cache;

in response to a determination that the Tag cache is full:

flush the Tag cache and a plurality of data keep caches;

after flushing the Tag cache and the plurality of data keep caches, store the physical location of the non-volatile memory that is associated with the data write in the Tag cache;

identify an edge wordline associated with an open memory block of the non-volatile memory;

store a physical location of the non-volatile memory that is associated with the edge wordline in the Tag cache; and

update, based on data stored at the physical location of the non-volatile memory that is associated with the edge wordline, an XOR sum stored in a data keep cache that is associated with the physical location of the memory that is associated with the edge wordline;

identify a data keep cache of the plurality of data keep caches that is associated with the data write based on the physical location of the non-volatile memory that is associated with the data write;

update an XOR sum stored in the identified data keep cache based on the data of the data write and the XOR sum that is stored in the identified data keep cache; and

store the updated XOR sum in the identified data keep cache.

10. The memory system of claim 9 , wherein the Tag cache comprises a first-in-first-out data cache.

11. The memory system of claim 9 , wherein the processor is further configured to:

determine that a failure occurred during the data write;

determine that the physical location of the non-volatile memory that is associated with the data write is stored in the Tag cache;

calculate the data associated with the data write based on the second XOR sum that is stored in the data keep cache associated with the physical location of the memory that is associated with the data write; and

restore the data associated with the data write to the physical location of the non-volatile memory.

12. The memory system of claim 11 , wherein the processor is further configured to:

determine a second physical location of the non-volatile memory that may have a potential error based on the determined failure at the physical location of the non-volatile memory;

identify a second data keep cache of the plurality of data keep caches that is associated with the second physical location of the non-volatile memory;

calculate data associated with the second physical location of the non-volatile memory based on an XOR sum that is stored in the second data keep cache;

compare the calculated data associated with the second physical location of the non-volatile memory to data that is stored at the second physical location of the non-volatile memory to determine whether the data that is stored at the second physical location of the non-volatile memory has been disturbed; and

restore the data stored at the second physical location of the non-volatile memory in response to determining that the data that is stored at the second physical location of the non-volatile memory has been disturbed.

13. The memory system of claim 9 , wherein the processor is further configured to:

determine a need to erase data that is stored at the physical location of the non-volatile memory;

determine whether the physical location of the non-volatile memory is stored in the Tag cache;

flush the Tag cache and the plurality of data keep caches in response to determining that the physical location of the non-volatile memory is stored in the Tag cache; and

erase data that is stored at the physical location of the non-volatile memory.

14. The memory system of claim 9 , wherein the processor is further configured to:

determine whether a number of data writes to the physical location of the non-volatile memory exceeds a threshold; and

disabling the plurality of data keep caches in response determining that the number of data writes to the physical location of the non-volatile memory exceeds the threshold.

15. The memory system of claim 9 , wherein the processor is further configured to:

dynamically adjust a size of the Tag cache or one or more data keep cache of the plurality of data keep caches based on a number of open data block in the storage device.