IP Library Granted Patent US 9,172,012
Granted Patent B2
US 9,172,012 · App. 13/796,045 · Granted Oct 27, 2015

Multi-chip light emitter packages and related methods

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Quick Facts
Patent No.
US 9,172,012
App. No.
13/796,045
Granted
Oct 27, 2015
Kind
B2
Abstract

Light emitter packages having multiple light emitter chips, such as light emitting diode (LED) chips, and related methods are provided. In one embodiment, a light emitter package can include a ceramic submount. An array of light emitter chips can be disposed over a portion of the submount, and each light emitter chip can include a horizontal chip structure having positive and negative electrical contacts disposed on a same side. The positive and negative electrical contacts can be adapted to electrically communicate to conductive portions of the submount. Light emitter packages can further include a lens overmolded on the submount and covering a portion of the array.

Claims (39)

1. A method of providing a light emitter package, the method comprising:

providing a submount having a planar upper surface;

providing an array of light emitter chips disposed over a portion of the planar upper surface of the submount in a rectangular arrangement;

connecting each light emitter chip of the array of light emitter chips to conductive portions of the submount via non-wire bond connections; and

providing a lens over the array of light emitter chips, wherein the lens is asymmetric about a central axis of the submount that is orthogonal to the planar upper surface of the submount.

2. The method of claim 1 , wherein directly connecting each light emitter chip comprises connecting the bottom side of each light emitter chip to conductive portions of the submount via a eutectic direct die attach process.

3. The method of claim 1 , wherein conductive portions of the submount comprise a positive contact pad, a negative contact pad, and at least one intermediate contact pad.

4. The method of claim 3 , further comprising providing portions of intermediate contact pad between portions of the positive and negative contact pads.

5. The package of claim 1 , wherein providing an asymmetric lens comprises overmolding the asymmetric lens.

6. The method of claim 1 , wherein each light emitter chip comprises a horizontal chip structure having positive and negative electrical contacts disposed on a same side.

7. The method of claim 6 , wherein the positive and negative electrical contacts are disposed on a bottom side of each light emitter chip.

8. A light emitter package comprising:

an array of light emitter chips disposed on a submount in a rectangular arrangement and connected without wire bonds, wherein the array of light emitter chips comprises a center point coincident with the center point of the submount;

a lens disposed over the array of light emitter chips, and wherein the lens is asymmetric about the center point of the array of light emitter chips; and

a positive electrical pad, an intermediate electrical pad, and a negative electrical pad.

9. The package of claim 8 , wherein a portion of the intermediate contact pad is disposed between portions of the positive and negative contact pads.

10. The package of claim 8 , wherein a portion of the positive contact pad is adjacent to a portion of the negative contact pad.

11. The package of claim 8 , wherein the positive contact pad is adjacent to intermediate contact pad along at least three sides.

12. The package of claim 8 , wherein the negative contact pad is adjacent to intermediate contact pad along at least three sides.

13. The package of claim 8 , wherein the array defines an LED chip-populated area having an aspect ratio greater than 1.

14. The package of claim 8 , wherein the array defines an LED chip-populated area having an aspect ratio greater than 2.

15. The package of claim 8 , wherein the array defines an LED chip-populated area having an aspect ratio greater than 3.

16. A light emitter package comprising:

a submount comprising a ceramic material having a planar upper surface;

an array of light emitter chips disposed on a portion of the planar upper surface of the submount, wherein each light emitter chip comprises a horizontal chip structure having positive and negative electrical contacts disposed on a same side, wherein the positive and negative electrical contacts are adapted to electrically communicate to conductive portions of the submount; and

a lens overmolded on the planar upper surface of the submount and covering a portion of the array, wherein the lens is asymmetric about a central axis of the submount that is orthogonal to the planar upper surface of the submount.

17. The package of claim 16 , wherein the package is adapted to deliver approximately 100 lumens per watt (LPW) or more at 1.5 amps (A) and/or 9 watts (W).

18. The package of claim 16 , wherein the package is configured to refract light emitted by the array of light emitter chips toward a preferential direction.

19. The package of claim 18 , wherein:

the array of light emitter chips defines an emitter axis; and

the lens has an outer surface and a centerline which is offset from the emitter axis toward the preferential direction.

20. The package of claim 1 , wherein the package comprises a first contact pad, a second contact pad, and a third contact pad.

21. The package of claim 20 , wherein each of the first, second, and third contact pads comprise centrally disposed leg portions.

22. The package of claim 21 , wherein leg portions of the second contact pad are disposed between leg portions of the first and third contact pads.

23. The package of claim 16 , wherein the light emitter chips comprise light emitting diode (LED) chips.

24. The package of claim 23 , wherein the LED chips are approximately 1000 μm×1000 μm in size.

25. The package of claim 23 , wherein the LED chips are approximately 350 μm ×350 μm in size.

26. The package of claim 23 , wherein the package comprises an array of eight LED chips.

27. The package of claim 23 , wherein the package comprises an array of forty-eight LED chips.

Assignments (5)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 058983/0001 Recorded Jun 25, 2025
From: CITIZENS BANK, N.A.
To: SMART MODULAR TECHNOLOGIES, INC.; SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; CREELED, INC.
Reel/Frame 071725/0207 →
SECURITY INTEREST Recorded Feb 7, 2022
From: SMART MODULAR TECHNOLOGIES, INC.; SMART HIGH RELIABILITY SOLUTIONS, LLC; SMART EMBEDDED COMPUTING, INC.; CREELED, INC.
To: CITIZENS BANK, N.A.
Reel/Frame 058983/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2021
From: CREE, INC.
To: CREELED, INC.
Reel/Frame 055780/0121 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2014
From: ANDREWS, PETER S.; WILCOX, KURT S.; LOWES, THEODORE; KELLER, BERND P.
To: CREE, INC.
Reel/Frame 034492/0748 →