Shared bit line string architecture
Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
1. A method for operating a shared bit line string architecture, comprising:
setting a selection even/odd string transistor into a conducting state, the selection even/odd string transistor is connected between a first string and a second string, the first string includes a first select transistor with a first threshold voltage, the second string includes a second select transistor with a second threshold voltage greater than the first threshold voltage, the first select transistor and the second select transistor are controlled by a drain-side select line, the first string includes a memory cell, the second select transistor includes a drain that is directly connected to a shared bit line, the selection even/odd string transistor is connected to the shared bit line and the first select transistor;
setting the drain-side select line to a voltage that is greater than the first threshold voltage and less than the second threshold voltage; and
performing an operation on the memory cell subsequent to the setting a selection even/odd string transistor into a conducting state.
2. The method of claim 1 , wherein:
the first select transistor includes a first drain, the selection even/odd string transistor is connected to the first drain and the drain of the second select transistor.
3. The method of claim 1 , wherein:
the performing an operation includes applying a selected word line voltage to the memory cell and a selected bit line voltage to the shared bit line, the operation comprises a programming operation, the selected word line voltage corresponds with a programming voltage.
4. The method of claim 1 , further comprising:
preparing the pair of strings for programming prior to the setting a selection even/odd string transistor into a conducting state.
5. The method of claim 4 , wherein:
the preparing the pair of strings for programming includes programming the selection even/odd string transistor to a third threshold voltage greater than the first threshold voltage, programming the first select transistor to the first threshold voltage, and programming the second select transistor to the second threshold voltage.
6. The method of claim 5 , wherein:
the third threshold voltage is different from the second threshold voltage.
7. The method of claim 1 , wherein:
the selection even/odd string transistor comprises a single gate-controlled device including more than two source/drain junctions.
8. The method of claim 1 , wherein:
the memory cell comprises a transistor including a charge storage layer.
9. The method of claim 8 , wherein:
the charge storage layer comprises a layer of silicon nitride.
10. The method of claim 1 , wherein:
the first string is associated with an odd bit line of a plurality of odd bit lines and the second string is associated with an even bit line of a plurality of even bit lines, the plurality of odd bit lines and the plurality of even bit lines are interdigitated.
11. A non-volatile storage system, comprising:
a semiconductor memory array, the semiconductor memory array includes a pair of strings and a string selection transistor, the pair of strings includes a first string and a second string, the first string includes a first select transistor with a first threshold voltage, the second string includes a second select transistor with a second threshold voltage greater than the first threshold voltage, the first select transistor and the second select transistor are controlled by a drain-side select line, the first string includes a memory cell, the second select transistor includes a drain that is directly connected to a shared bit line, the string selection transistor is connected to the shared bit line and the first select transistor; and
one or more managing circuits in communication with the semiconductor memory array, the one or more managing circuits cause the string selection transistor to be set into a conducting state, the one or more managing circuits cause the drain-side select line to be set to a voltage that is greater than the first threshold voltage and less than the second threshold voltage, the one or more managing circuits cause an operation to be performed on the memory cell subsequent to setting the string selection transistor into the conducting state.
12. The non-volatile storage system of claim 11 , wherein:
the operation comprises a programming operation that includes applying a selected bit line voltage to the shared bit line.
13. The non-volatile storage system of claim 11 , wherein:
the one or more managing circuits cause the first select transistor to be programmed to the first threshold voltage and the second select transistor to be programmed to the second threshold voltage prior to setting the string selection transistor into the conducting state.
14. The non-volatile storage system of claim 11 , wherein:
the string selection transistor comprises a gate-controlled device including more than two source/drain junctions.
15. The non-volatile storage system of claim 11 , wherein:
the memory cell comprises a transistor including a charge storage layer.
16. The non-volatile storage system of claim 15 , wherein:
the charge storage layer comprises a layer of silicon nitride.
17. A method for operating a shared bit line string architecture, comprising:
acquiring a command;
determining a memory cell to be operated on based on the command, the memory cell is associated with a first string of a pair of strings, the pair of strings includes the first string and a second string, the first string includes a first select transistor associated with a first threshold voltage, the second string includes a second select transistor associated with a second threshold voltage, the first select transistor and the second select transistor are controlled by a drain-side select line;
setting a selection even/odd string transistor into a conducting state, the selection even/odd string transistor is connected to the first select transistor and the second select transistor, the selection even/odd string transistor comprises a single gate-controlled device including more than two source/drain junctions;
setting the drain-side select line to a voltage that is greater than the first threshold voltage and less than the second threshold voltage; and
performing an operation on the memory cell subsequent to the setting the drain-side select line.
18. The method of claim 17 , wherein:
the operation comprises a programming operation.
19. The method of claim 18 , further comprising:
preparing the pair of strings for programming prior to the setting a selection even/odd string transistor into a conducting state, the preparing the pair of strings for programming includes programming the selection even/odd string transistor to the first threshold voltage, programming the first select transistor to the first threshold voltage, and programming the second select transistor to the second threshold voltage.
20. The method of claim 19 , wherein:
the memory cell comprises a transistor including a charge storage layer.