IP Library Granted Patent US 8,507,922
Granted Patent B2
US 8,507,922 · App. 13/808,556 · Granted Aug 13, 2013

Silicon carbide substrate, semiconductor device, and SOI wafer

Inventors: Satoshi Kawamoto (Okayama, JP); Masaki Nakamura (Okayama, JP)
Assignees: Mitsui Engineering & Shipbuilding Co., Ltd.; Admap Inc.
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Quick Facts
Patent No.
US 8,507,922
App. No.
13/808,556
Granted
Aug 13, 2013
Kind
B2
Abstract

Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer ( 1 ), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer ( 2 ), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer ( 2 ) has a high-frequency loss smaller than that of the first silicon carbide layer ( 1 ), the first silicon carbide layer ( 1 ) has a thermal conductivity higher than that of the second silicon carbide layer ( 2 ), and on the surface side of the second silicon carbide layer ( 2 ), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more.

Claims (26)

1. A silicon carbide substrate for mounting an element operating in a high-frequency region on a surface thereof, said silicon carbide substrate comprising:

a first layer composed of polycrystalline silicon carbide; and

a second layer composed of polycrystalline silicon carbide and formed on a surface of said first layer and on the surface side of said silicon carbide substrate,

wherein said second layer has a thickness of 10 μm or more accounting for up to 20% of a total thickness of said silicon carbide substrate and has a less high-frequency loss than said first layer, and said first layer has a higher thermal conductivity than said second layer.

2. The silicon carbide substrate according to claim 1 , whose high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less on a surface side of said second layer and whose thermal conductivity is 200 W/mK or more.

3. The silicon carbide substrate according to claim 1 , wherein said first layer is formed by a chemical vapor deposition process in an atmosphere containing nitrogen and said second layer is formed by the chemical vapor deposition process in an atmosphere containing no nitrogen.

4. A semiconductor device comprising:

the silicon carbide substrate according to claim 1 ; and

a semiconductor element joined to a surface of said second layer of said silicon carbide substrate.

5. An SOI wafer comprising:

the silicon carbide substrate according to claim 1 ;

an insulating layer formed on a surface of said second layer of said silicon carbide substrate; and

a silicon layer formed on a surface of said insulating layer.

6. A silicon carbide substrate for mounting an element operating in a high-frequency region on a surface thereof, said silicon carbide substrate comprising:

a first layer composed of polycrystalline silicon carbide; and

a second layer composed of polycrystalline silicon carbide and formed on a surface of said first layer and on the surface side of said silicon carbide substrate,

wherein said second layer has a higher specific resistance than said first layer and said first layer has a higher thermal conductivity than said second layer, and

wherein specific resistance of said silicon carbide substrate is 10 4 Ωcm or more on a surface side of said second layer and thermal conductivity of said silicon carbide substrate is 200W/mK or more.

7. The silicon carbide substrate according to claim 6 , wherein said first layer is formed by a chemical vapor deposition process in an atmosphere containing nitrogen and said second layer is formed by the chemical vapor deposition process in an atmosphere containing no nitrogen.

8. A semiconductor device comprising:

the silicon carbide substrate according to claim 6 ; and

a semiconductor element joined to a surface of said second layer of said silicon carbide substrate.

9. An SOI wafer comprising:

the silicon carbide substrate according to claim 6 ;

an insulating layer formed on a surface of said second layer of said silicon carbide substrate; and

a silicon layer formed on a surface of said insulating layer.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2023
From: FERROTEC HOLDINGS CORPORATION
To: FERROTEC MATERIAL TECHNOLOGIES CORPORATION
Reel/Frame 063343/0210 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 050370 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 19, 2019
From: MITSUI E&S MACHINERY CO., LTD.
To: FERROTEC HOLDINGS CORPORATION
Reel/Frame 050441/0158 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2019
From: MITSUI E&S MACHINERY CO., LTD.
To: FERROTEC HOLDINGS CORPORATION
Reel/Frame 050370/0773 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2019
From: ADMAP, INC.
To: MITSUI E&S MACHINERY CO., LTD.
Reel/Frame 050215/0333 →
CHANGE OF NAME Recorded Aug 9, 2018
From: MITSUI ENGINEERING & SHIPBUILDING CO., LTD.
To: MITSUI E&S MACHINERY CO., LTD.
Reel/Frame 046755/0011 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2013
From: KAWAMOTO, SATOSHI; NAKAMURA, MASAKI
To: MITSUI ENGINEERING & SHIPBUILDING CO., LTD; ADMAP INC
Reel/Frame 029588/0290 →
Priority Claims (1)
JP 2010-153730 · Jul 6, 2010 · national
Continuity (1)
Related Publication 20130112997A1 · May 9, 2013