Method for reducing effective raw bit error rate in multi-level cell NAND flash memory
View Patent ↗A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.
1. A memory system comprising:
a flash subsystem for storing data grouped into pages including error correcting code (ECC), the pages of data being identified by page numbers;
a central processing unit (CPU) coupled to the flash subsystem;
a flash controller coupled to the CPU, the CPU configured to pair a lower page of data with an upper page of data the flash controller configured to split the ECC; and
a buffer including a page of data, the page of data having an upper page of data and a lower page of data and to be programmed in the flash subsystem, wherein at least a segment of the upper page of data or at least a segment of the lower of data are concatenated with a split ECC.
2. The memory system, as recited in claim 1 , wherein the flash controller is configured to compute the split ECC for concatenation and a split ECC being concatenated with the segment of a lower page of data and another split ECC being concatenated with the segment of the upper page of data.
3. The memory system, as recited in claim 1 , wherein the flash controller is configured to write pages comprising split segments and associated split ECC to the flash subsystem in sequential order.
4. The memory system, as recited in claim 1 , wherein the buffer is a flash-backed memory.
5. The memory system, as recited in claim 1 , wherein the buffer is a magnetic random access memory (MRAM).
6. The memory system, as recited in claim 5 , wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).
7. The memory system, as recited in claim 1 , wherein the flash subsystem includes more than one flash dice and is organized into blocks and a first block is in a first flash die and a second block is in a second flash die, further wherein the lower page of data in the first block is paired with the upper page of data in the second block and the upper page of data in the first block is paired with lower pages of data in the second block thereby allowing substantially concurrent read of the split at least one segment of the lower or upper page and the split ECC.
8. The memory system, as recited in claim 7 , wherein the first flash die and the second flash die are coupled to different flash channels.
9. The memory system, as recited in claim 1 , wherein the error correction code (ECC) is a Bose, Chaudhuri, and Hocquenghem (BCH) code.
10. The memory system, as recited in claim 1 , wherein the error correction code (ECC) is a low-density parity-check (LDPC) code.
11. A memory system comprising:
a flash subsystem for storing data grouped into pages including error correcting code (ECC), the pages of data being identified by page numbers;
a central processing unit (CPU) coupled to the flash subsystem;
a flash controller coupled to the CPU, the CPU being configured to pair a lower page of data with an upper page of data; and
a buffer including a page of data, the page of data having at least a segment of an upper page of data and a at least a segment of a lower page of data and to be programmed in the flash subsystem, wherein the upper or lower page of data are concatenated with a split ECC.
12. The memory system, as recited in claim 11 , wherein the flash controller is configured to compute the split ECC for concatenation and a split ECC being concatenated with the segment of a lower page of data and another split ECC being concatenated with the segment of the upper page of data.
13. The memory system, as recited in claim 11 , wherein the flash controller is configured to write pages comprising segments and associated split ECC to the flash subsystem in sequential order.
14. The memory system, as recited in claim 11 , wherein the buffer is a flash-backed memory.
15. The memory system, as recited in claim 11 , wherein the buffer is an magnetic random access memory (MRAM).
16. The memory system, as recited in claim 15 , wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).
17. The memory system, as recited in claim 11 , wherein the flash subsystem includes more than one flash dice and is organized into blocks and a first block is in a first flash die and a second block is in a second flash die, further wherein the lower page of data in the first block is paired with the upper page of data in the second block and the upper page of data in the first block is paired with lower pages of data in the second block thereby allowing substantially concurrent read of the split at least one segment of the lower or upper page and the split ECC.
18. The memory system, as recited in claim 17 , wherein the first flash die and the second flash die are coupled to different flash channels.
19. The memory system, as recited in claim 11 , wherein the error correction code (ECC) is a Bose, Chaudhuri, and Hocquenghem (BCH) code.
20. The memory system, as recited in claim 11 , wherein the error correction code (ECC) is a low-density parity-check (LDPC) code.
21. The memory system, as recited in claim 1 , wherein the flash subsystem is organized into blocks.
22. The memory system, as recited in claim 1 , wherein the upper page of data and the lower page of data are paired together.
23. The memory system, as recited in claim 11 , wherein the flash subsystem is organized into blocks.
24. The memory system, as recited in claim 11 , wherein the upper page of data and the lower page of data are paired together.