Flash memory techniques for recovering from write interrupt resulting from voltage fault
Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.
1. A memory device comprising:
a memory controller;
a non-volatile memory array for storing page data, the page data comprising upper-page data and lower-page data;
an on-chip cache configured to concurrently retain, until a first sector of upper-page data and a second sector of lower-page data are confirmed as written, a safe copy of at least a portion of the first sector of upper-page data and a safe copy of at least a portion of the second sector of lower-page data to be written to a respective group of cells of the memory array;
a host interface communicatively coupled with the memory controller and the non-volatile memory array, the host interface configured to accept a memory voltage supplied by a host for writing data to the non-volatile memory array; wherein,
the memory controller is configured to control a response to an occurrence of a write-interrupt resulting from a voltage fault in the memory voltage, the response comprising:
writing to the non-volatile memory array, after the memory voltage is verified as being within an acceptable range, one or more of the safe copy of the portion of the first sector of upper-page data and the safe copy of the portion of the second sector of lower-page data; and
terminating the write-interrupt.
2. The memory device of claim 1 , wherein the response avoids outputting of an error signal to the host.
3. The memory device of claim 1 , wherein terminating the write-interrupt comprises receiving new data from the host.
4. The memory device of claim 1 , wherein the voltage fault comprises a voltage value below a minimum specified regulated memory voltage and above a reset voltage value.
5. The memory device of claim 4 , wherein the response further comprises verifying, prior to writing to the non-volatile memory array, that a hard reset has not occurred.
6. The memory device of claim 5 , wherein the response further comprises verifying, prior to writing to the non-volatile memory array, that the memory voltage is above the minimum specified regulated memory voltage.
7. The memory device of claim 1 , wherein the non-volatile memory is configured as a single level cell memory.
8. The memory device of claim 1 , wherein the non-volatile memory is configured as a multi-level cell memory, and the page data further comprises middle-page data.
9. The memory device of claim 1 , further comprising a page buffer, including an upper page data latch and a lower page data latch communicatively coupled to the non-volatile memory array, and an external data latch communicatively coupled to the memory controller and the page buffer.
10. The memory device of claim 1 , wherein the response further comprises reconstructing a full page of data from (i) one or both of the safe copy of the portion of the first sector of upper-page data and the safe copy of the portion of the second sector of lower-page data and (ii) a partial page written to the non-volatile memory array.
11. A method for controlling data transfer from a host to a nonvolatile memory array, the method comprising:
receiving page data, the page data comprising lower-page data and upper-page data from a host;
maintaining at least some of the lower-page data and the upper-page data in an on-chip cache configured to concurrently retain, until a first sector of upper-page data and a second sector of lower-page data are confirmed as written, a safe copy of at least a first portion of the first sector of upper-page data and a safe copy of at least a portion of the second sector of lower-page data to be written to a respective group of cells of the memory array;
accepting, at a host interface, a memory voltage supplied by the host for writing data to the non-volatile memory array, the host interface communicatively coupled with the memory controller and the non-volatile memory array;
sensing an occurrence of a write-interrupt resulting from a voltage fault in the memory voltage and, in response to the occurrence, writing to the non-volatile memory array, after the memory voltage is verified as being within an acceptable range, one or more of the safe copy of the portion of the first sector of upper-page data and the safe copy of the portion of the second section of lower-page data; and
terminating the write-interrupt.
12. The method of claim 11 , wherein the response avoids outputting of an error signal to the host.
13. The method of claim 11 , wherein terminating the write-interrupt comprises receiving new data from the host.
14. The method of claim 11 , wherein the voltage fault comprises a voltage value below a minimum specified regulated memory voltage and above a reset voltage value.
15. The method of claim 14 , wherein the response further comprises verifying, prior to writing to the non-volatile memory array, that a hard reset has not occurred.
16. The method of claim 15 , wherein the response further comprises verifying, prior to writing to the non-volatile memory array, that the memory voltage is above the minimum specified regulated memory voltage.
17. A non-transitory computer-readable storage medium having stored thereon instructions which, when executed by a controller, cause the controller to perform operations, the operations comprising:
receiving page data, the page data comprising lower-page data and upper-page data from a host;
maintaining at least some of the lower-page data and the upper-page data in an on-chip cache configured to concurrently retain, until a first sector of upper-page data and a second sector of lower-page data are confirmed as written, a safe copy of at least a first portion of the first sector of upper-page data and a safe copy of at least a portion of the second sector of lower-page data to be written to a respective group of cells of the memory array;
accepting, at a host interface, a memory voltage supplied by the host for writing data to the non-volatile memory array, the host interface communicatively coupled with the memory controller and the non-volatile memory array;
sensing an occurrence of a write-interrupt resulting from a voltage fault in the memory voltage and, in response to the occurrence, writing to the non-volatile memory array, after the memory voltage is verified as being within an acceptable range, one or more of the safe copy of the portion of the first sector of upper-page data and the safe copy of the portion of the second section of lower-page data; and
terminating the write-interrupt.
18. The method of claim 17 , wherein the response avoids outputting of an error signal to the host.
19. The method of claim 17 , wherein terminating the write-interrupt comprises receiving new data from the host.
20. The method of claim 17 , wherein the voltage fault comprises a voltage value below a minimum specified regulated memory voltage and above a reset voltage value.