Self aligned embedded gate carbon transistors
Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.
1. A method for forming a transistor, comprising:
forming a gate structure embedded in a recess in a substrate, comprising:
forming a nitride layer over the substrate and in the recess;
depositing a gate material over the nitride layer; and
polishing the gate material and nitride layer to remove any such material that is outside the recess;
removing substrate material around the gate structure to create self-aligned source and drain recesses;
forming a channel layer over the gate structure and the source and drain recesses; and
forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.
2. The method of claim 1 , wherein the channel layer comprises a carbon-based channel material.
3. The method of claim 1 , further comprising forming the substrate, wherein the step of forming the substrate comprises:
etching a first substrate material layer to form trenches; and
depositing a second substrate material layer in the trenches to form dummy contacts that are separated and surrounded by the first material.
4. The method of claim 3 , further comprising removing the first substrate material that separates the regions of the second substrate material to form a recess in the substrate.
5. The method of claim 4 , wherein removing substrate material around the gate structure comprises removing the second substrate material to create the self-aligned source and drain recesses.
6. The method of claim 1 , further comprising forming a high-k dielectric layer over the gate structure and in the source and drain recesses.
7. The method of claim 6 , further comprising depositing a filler material in the source and drain recesses to protect the high-k dielectric layer.
8. The method of claim 7 , further comprising removing the filler material from the source and drain recesses prior to forming source and drain contacts.
9. The method of claim 1 , further comprising etching holes in the channel layer to provide access to the source and drain regions prior to forming the source and drain contacts.
10. The method of claim 1 , further comprising forming a passivation layer over the channel layer, wherein the source and drain contacts are accessible through the passivation layer.
11. A method for forming a transistor, comprising:
forming a substrate, comprising:
etching a first substrate material layer to form trenches; and
depositing a second substrate material layer in the trenches to form dummy contacts that are separated and surrounded by the first material;
forming a gate structure embedded in a recess in the substrate, comprising:
removing the first substrate material separating the regions of the second substrate material to form a recess in the substrate;
forming a nitride layer over the substrate and in the recess; and
depositing a gate material over the nitride layer; and polishing the gate material and nitride layer to remove any material outside the recess;
removing substrate material around the gate structure to create self-aligned source and drain recesses;
forming a carbon-based channel layer over the gate structure and the source and drain recesses; and
forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.