Defective P-N junction for backgated fully depleted silicon on insulator MOSFET
Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
1. A method for semiconductor fabrication, comprising:
forming a well in a semiconductor substrate, the semiconductor substrate including a semiconductor on insulator (SOI) layer present on a buried dielectric layer, the buried dielectric layer being present on a base semiconductor layer, wherein the well region is present within the base semiconductor layer;
forming a pocket within the well region directly underlying the buried dielectric layer, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket;
creating defects at the p-n junction such that a leakage resistance of the p-n junction is decreased.
2. The method as recited in claim 1 , wherein creating defects includes creating defects as part of a same implantation used to form the pocket.
3. The method as recited in claim 1 , wherein creating defects includes using a same mask used to form the pocket to apply a separate implantation.
4. The method as recited in claim 1 , wherein creating defects includes performing a blanket implantation over the substrate.
5. The method as recited in claim 1 , wherein the defects include end-of-range implant defects.
6. The method as recited in claim 1 , wherein the defects include impurities that generate mid-gap states.
7. The method as recited in claim 1 , wherein creating defects includes creating defects inside a depletion region associated with the p-n junction.
8. A method for semiconductor fabrication, comprising:
forming a well in a semiconductor substrate;
forming a pocket within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket, wherein the pocket is formed directly under an isolation layer or LUG semiconductor substrate;
creating defects at the p-n junction such that a leakage resistance of the p-n junction is decreased, wherein the defects are created as part of a same implantation used to form the pocket.
9. The method as recited in claim 8 , wherein the same implantation includes using a same mask used to form the pocket.
10. The method as recited in claim 8 , wherein the defects include end-of-range implant defects.
11. The method as recited in claim 8 , wherein the defects include impurities that generate mid-gap states.
12. The method as recited in claim 8 , wherein creating defects includes creating defects inside a depletion region associated with the p-n junction.
13. The method as recited in claim 8 , wherein the isolation layer includes a buried oxide (BOX) layer and the semiconductor substrate includes a silicon-on-insulator (SOI) layer formed over the BOX layer.
14. A semiconductor device, comprising:
a semiconductor substrate having a well formed therein, the semiconductor substrate including a semiconductor on insulator (SOI) layer present on a buried dielectric layer, the buried dielectric layer being present on a base semiconductor layer, wherein the well region is present within the base semiconductor layer;
a pocket formed within the well directly underlying the buried dielectric layer, the pocketing having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket; and
defects created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
15. The semiconductor device as recited in claim 14 , wherein defects are created inside a depletion region associated with the p-n junction.
16. The semiconductor device as recited in claim 14 , wherein the semiconductor substrate includes a semiconductor-on-insulator (SOI) layer formed over a buried dielectric layer.
17. The semiconductor device as recited in claim 16 , wherein the SOI layer includes an ultrathin SOI layer.