Physical unclonable function generation and management
Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.
1. A circuit authentication system comprising:
a plurality of physical unclonable function (PUF) elements including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, wherein the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements;
a measurement unit configured to measure at least one differential of states between said first subset of PUF elements and said second subset of PUF elements at respective intermediate connection points between two serially connected PUF elements in the first subset and between two serially connected PUF elements in the second subset, said at least one differential of states forming a basis of at least part of a bit sequence of an authentication signature for said circuit; and
a filter configured to filter unreliable states determined by the measurement unit by replacing said unreliable states with predetermined bits,
wherein the first subset and the second subset exclude current mirrors.
2. The circuit authentication system of claim 1 , wherein said plurality of PUF elements include at least one of transistors, diodes or resistors.
3. The circuit authentication system of claim 1 , wherein said plurality of PUF elements include transistors arranged in a diode configuration.
4. The circuit authentication system of claim 1 , wherein said measurement unit comprises at least one quantizer configured to assess whether each of the differentials of states is a one or a zero in said bit sequence.
5. The circuit authentication system of claim 1 , further comprising a multiplexer configured to combine said states to generate a total number of said differentials of states that is larger than a total number of PUF elements in said plurality of PUF elements.
6. The circuit authentication system of claim 1 , further comprising a plurality of additional PUF elements configured to have an additional differential voltage applied thereto, wherein the measurement unit is configured to determine the filtered unreliable states by employing measurements of said additional PUF elements obtained with said additional differential voltage applied thereto.
7. The circuit authentication system of claim 1 , wherein the plurality of PUF elements consist of resistors.
8. The circuit authentication system of claim 1 , further comprising a multiplexer configured to combine said states, wherein said measurement unit comprises at least one quantizer configured to assess whether each of the differentials of states is a one or a zero in said bit sequence, and wherein the multiplexer, the at least one quantizer, and at least some of the PUF elements are each connected to a same regulated voltage.